// SPDX-License-Identifier: (GPL-2.0+ or MIT)
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/*
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* Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
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*/
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#ifndef _DT_BINDINGS_RESET_SUN50I_H6_H_
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#define _DT_BINDINGS_RESET_SUN50I_H6_H_
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#define RST_MBUS 0
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#define RST_BUS_DE 1
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#define RST_BUS_DEINTERLACE 2
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#define RST_BUS_GPU 3
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#define RST_BUS_CE 4
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#define RST_BUS_VE 5
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#define RST_BUS_EMCE 6
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#define RST_BUS_VP9 7
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#define RST_BUS_DMA 8
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#define RST_BUS_MSGBOX 9
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#define RST_BUS_SPINLOCK 10
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#define RST_BUS_HSTIMER 11
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#define RST_BUS_DBG 12
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#define RST_BUS_PSI 13
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#define RST_BUS_PWM 14
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#define RST_BUS_IOMMU 15
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#define RST_BUS_DRAM 16
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#define RST_BUS_NAND 17
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#define RST_BUS_MMC0 18
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#define RST_BUS_MMC1 19
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#define RST_BUS_MMC2 20
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#define RST_BUS_UART0 21
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#define RST_BUS_UART1 22
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#define RST_BUS_UART2 23
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#define RST_BUS_UART3 24
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#define RST_BUS_I2C0 25
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#define RST_BUS_I2C1 26
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#define RST_BUS_I2C2 27
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#define RST_BUS_I2C3 28
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#define RST_BUS_SCR0 29
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#define RST_BUS_SCR1 30
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#define RST_BUS_SPI0 31
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#define RST_BUS_SPI1 32
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#define RST_BUS_EMAC 33
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#define RST_BUS_TS 34
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#define RST_BUS_IR_TX 35
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#define RST_BUS_THS 36
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#define RST_BUS_I2S0 37
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#define RST_BUS_I2S1 38
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#define RST_BUS_I2S2 39
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#define RST_BUS_I2S3 40
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#define RST_BUS_SPDIF 41
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#define RST_BUS_DMIC 42
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#define RST_BUS_AUDIO_HUB 43
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#define RST_USB_PHY0 44
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#define RST_USB_PHY1 45
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#define RST_USB_PHY3 46
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#define RST_USB_HSIC 47
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#define RST_BUS_OHCI0 48
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#define RST_BUS_OHCI3 49
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#define RST_BUS_EHCI0 50
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#define RST_BUS_XHCI 51
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#define RST_BUS_EHCI3 52
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#define RST_BUS_OTG 53
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#define RST_BUS_PCIE 54
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#define RST_PCIE_POWERUP 55
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#define RST_BUS_HDMI 56
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#define RST_BUS_HDMI_SUB 57
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#define RST_BUS_TCON_TOP 58
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#define RST_BUS_TCON_LCD0 59
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#define RST_BUS_TCON_TV0 60
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#define RST_BUS_CSI 61
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#define RST_BUS_HDCP 62
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#endif /* _DT_BINDINGS_RESET_SUN50I_H6_H_ */
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