/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
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/*
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* Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com>
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*/
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#ifndef _DT_BINDINGS_RESET_SUN50I_A100_H_
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#define _DT_BINDINGS_RESET_SUN50I_A100_H_
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#define RST_MBUS 0
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#define RST_BUS_DE 1
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#define RST_BUS_G2D 2
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#define RST_BUS_GPU 3
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#define RST_BUS_CE 4
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#define RST_BUS_VE 5
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#define RST_BUS_DMA 6
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#define RST_BUS_MSGBOX 7
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#define RST_BUS_SPINLOCK 8
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#define RST_BUS_HSTIMER 9
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#define RST_BUS_DBG 10
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#define RST_BUS_PSI 11
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#define RST_BUS_PWM 12
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#define RST_BUS_DRAM 13
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#define RST_BUS_NAND 14
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#define RST_BUS_MMC0 15
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#define RST_BUS_MMC1 16
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#define RST_BUS_MMC2 17
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#define RST_BUS_UART0 18
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#define RST_BUS_UART1 19
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#define RST_BUS_UART2 20
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#define RST_BUS_UART3 21
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#define RST_BUS_UART4 22
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#define RST_BUS_I2C0 23
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#define RST_BUS_I2C1 24
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#define RST_BUS_I2C2 25
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#define RST_BUS_I2C3 26
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#define RST_BUS_SPI0 27
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#define RST_BUS_SPI1 28
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#define RST_BUS_SPI2 29
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#define RST_BUS_EMAC 30
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#define RST_BUS_IR_RX 31
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#define RST_BUS_IR_TX 32
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#define RST_BUS_GPADC 33
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#define RST_BUS_THS 34
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#define RST_BUS_I2S0 35
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#define RST_BUS_I2S1 36
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#define RST_BUS_I2S2 37
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#define RST_BUS_I2S3 38
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#define RST_BUS_SPDIF 39
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#define RST_BUS_DMIC 40
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#define RST_BUS_AUDIO_CODEC 41
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#define RST_USB_PHY0 42
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#define RST_USB_PHY1 43
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#define RST_BUS_OHCI0 44
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#define RST_BUS_OHCI1 45
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#define RST_BUS_EHCI0 46
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#define RST_BUS_EHCI1 47
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#define RST_BUS_OTG 48
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#define RST_BUS_LRADC 49
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#define RST_BUS_DPSS_TOP0 50
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#define RST_BUS_DPSS_TOP1 51
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#define RST_BUS_MIPI_DSI 52
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#define RST_BUS_TCON_LCD 53
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#define RST_BUS_LVDS 54
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#define RST_BUS_LEDC 55
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#define RST_BUS_CSI 56
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#define RST_BUS_CSI_ISP 57
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#endif /* _DT_BINDINGS_RESET_SUN50I_A100_H_ */
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