/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */
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/*
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* Realtek RTD1195 reset controllers
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*
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* Copyright (c) 2017 Andreas Färber
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*/
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#ifndef DT_BINDINGS_RESET_RTD1195_H
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#define DT_BINDINGS_RESET_RTD1195_H
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/* soft reset 1 */
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#define RTD1195_RSTN_MISC 0
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#define RTD1195_RSTN_RNG 1
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#define RTD1195_RSTN_USB3_POW 2
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#define RTD1195_RSTN_GSPI 3
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#define RTD1195_RSTN_USB3_P0_MDIO 4
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#define RTD1195_RSTN_VE_H265 5
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#define RTD1195_RSTN_USB 6
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#define RTD1195_RSTN_USB_PHY0 8
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#define RTD1195_RSTN_USB_PHY1 9
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#define RTD1195_RSTN_HDMIRX 11
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#define RTD1195_RSTN_HDMI 12
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#define RTD1195_RSTN_ETN 14
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#define RTD1195_RSTN_AIO 15
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#define RTD1195_RSTN_GPU 16
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#define RTD1195_RSTN_VE_H264 17
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#define RTD1195_RSTN_VE_JPEG 18
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#define RTD1195_RSTN_TVE 19
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#define RTD1195_RSTN_VO 20
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#define RTD1195_RSTN_LVDS 21
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#define RTD1195_RSTN_SE 22
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#define RTD1195_RSTN_DCU 23
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#define RTD1195_RSTN_DC_PHY 24
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#define RTD1195_RSTN_CP 25
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#define RTD1195_RSTN_MD 26
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#define RTD1195_RSTN_TP 27
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#define RTD1195_RSTN_AE 28
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#define RTD1195_RSTN_NF 29
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#define RTD1195_RSTN_MIPI 30
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/* soft reset 2 */
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#define RTD1195_RSTN_ACPU 0
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#define RTD1195_RSTN_VCPU 1
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#define RTD1195_RSTN_PCR 9
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#define RTD1195_RSTN_CR 10
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#define RTD1195_RSTN_EMMC 11
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#define RTD1195_RSTN_SDIO 12
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#define RTD1195_RSTN_I2C_5 18
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#define RTD1195_RSTN_RTC 20
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#define RTD1195_RSTN_I2C_4 23
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#define RTD1195_RSTN_I2C_3 24
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#define RTD1195_RSTN_I2C_2 25
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#define RTD1195_RSTN_I2C_1 26
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#define RTD1195_RSTN_UR1 28
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/* soft reset 3 */
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#define RTD1195_RSTN_SB2 0
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/* iso soft reset */
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#define RTD1195_ISO_RSTN_VFD 0
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#define RTD1195_ISO_RSTN_IR 1
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#define RTD1195_ISO_RSTN_CEC0 2
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#define RTD1195_ISO_RSTN_CEC1 3
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#define RTD1195_ISO_RSTN_DP 4
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#define RTD1195_ISO_RSTN_CBUSTX 5
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#define RTD1195_ISO_RSTN_CBUSRX 6
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#define RTD1195_ISO_RSTN_EFUSE 7
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#define RTD1195_ISO_RSTN_UR0 8
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#define RTD1195_ISO_RSTN_GMAC 9
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#define RTD1195_ISO_RSTN_GPHY 10
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#define RTD1195_ISO_RSTN_I2C_0 11
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#define RTD1195_ISO_RSTN_I2C_6 12
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#define RTD1195_ISO_RSTN_CBUS 13
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#endif
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