/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
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/*
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* Copyright (c) 2019 BayLibre, SAS.
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* Author: Jerome Brunet <jbrunet@baylibre.com>
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*
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*/
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#ifndef _DT_BINDINGS_AMLOGIC_MESON_G12A_RESET_H
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#define _DT_BINDINGS_AMLOGIC_MESON_G12A_RESET_H
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/* RESET0 */
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#define RESET_HIU 0
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/* 1 */
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#define RESET_DOS 2
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/* 3-4 */
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#define RESET_VIU 5
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#define RESET_AFIFO 6
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#define RESET_VID_PLL_DIV 7
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/* 8-9 */
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#define RESET_VENC 10
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#define RESET_ASSIST 11
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#define RESET_PCIE_CTRL_A 12
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#define RESET_VCBUS 13
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#define RESET_PCIE_PHY 14
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#define RESET_PCIE_APB 15
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#define RESET_GIC 16
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#define RESET_CAPB3_DECODE 17
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/* 18 */
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#define RESET_HDMITX_CAPB3 19
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#define RESET_DVALIN_CAPB3 20
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#define RESET_DOS_CAPB3 21
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/* 22 */
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#define RESET_CBUS_CAPB3 23
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#define RESET_AHB_CNTL 24
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#define RESET_AHB_DATA 25
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#define RESET_VCBUS_CLK81 26
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/* 27-31 */
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/* RESET1 */
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/* 32 */
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#define RESET_DEMUX 33
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#define RESET_USB 34
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#define RESET_DDR 35
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/* 36 */
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#define RESET_BT656 37
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#define RESET_AHB_SRAM 38
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/* 39 */
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#define RESET_PARSER 40
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/* 41 */
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#define RESET_ISA 42
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#define RESET_ETHERNET 43
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#define RESET_SD_EMMC_A 44
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#define RESET_SD_EMMC_B 45
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#define RESET_SD_EMMC_C 46
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/* 47 */
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#define RESET_USB_PHY20 48
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#define RESET_USB_PHY21 49
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/* 50-60 */
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#define RESET_AUDIO_CODEC 61
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/* 62-63 */
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/* RESET2 */
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/* 64 */
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#define RESET_AUDIO 65
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#define RESET_HDMITX_PHY 66
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/* 67 */
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#define RESET_MIPI_DSI_HOST 68
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#define RESET_ALOCKER 69
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#define RESET_GE2D 70
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#define RESET_PARSER_REG 71
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#define RESET_PARSER_FETCH 72
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#define RESET_CTL 73
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#define RESET_PARSER_TOP 74
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/* 75-77 */
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#define RESET_DVALIN 78
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#define RESET_HDMITX 79
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/* 80-95 */
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/* RESET3 */
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/* 96-95 */
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#define RESET_DEMUX_TOP 105
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#define RESET_DEMUX_DES_PL 106
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#define RESET_DEMUX_S2P_0 107
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#define RESET_DEMUX_S2P_1 108
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#define RESET_DEMUX_0 109
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#define RESET_DEMUX_1 110
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#define RESET_DEMUX_2 111
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/* 112-127 */
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/* RESET4 */
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/* 128-129 */
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#define RESET_MIPI_DSI_PHY 130
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/* 131-132 */
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#define RESET_RDMA 133
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#define RESET_VENCI 134
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#define RESET_VENCP 135
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/* 136 */
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#define RESET_VDAC 137
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/* 138-139 */
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#define RESET_VDI6 140
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#define RESET_VENCL 141
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#define RESET_I2C_M1 142
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#define RESET_I2C_M2 143
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/* 144-159 */
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/* RESET5 */
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/* 160-191 */
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/* RESET6 */
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#define RESET_GEN 192
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#define RESET_SPICC0 193
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#define RESET_SC 194
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#define RESET_SANA_3 195
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#define RESET_I2C_M0 196
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#define RESET_TS_PLL 197
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#define RESET_SPICC1 198
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#define RESET_STREAM 199
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#define RESET_TS_CPU 200
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#define RESET_UART0 201
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#define RESET_UART1_2 202
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#define RESET_ASYNC0 203
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#define RESET_ASYNC1 204
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#define RESET_SPIFC0 205
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#define RESET_I2C_M3 206
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/* 207-223 */
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/* RESET7 */
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#define RESET_USB_DDR_0 224
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#define RESET_USB_DDR_1 225
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#define RESET_USB_DDR_2 226
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#define RESET_USB_DDR_3 227
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#define RESET_TS_GPU 228
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#define RESET_DEVICE_MMC_ARB 229
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#define RESET_DVALIN_DMC_PIPL 230
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#define RESET_VID_LOCK 231
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#define RESET_NIC_DMC_PIPL 232
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#define RESET_DMC_VPU_PIPL 233
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#define RESET_GE2D_DMC_PIPL 234
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#define RESET_HCODEC_DMC_PIPL 235
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#define RESET_WAVE420_DMC_PIPL 236
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#define RESET_HEVCF_DMC_PIPL 237
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/* 238-255 */
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#endif
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