/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Device Tree binding constants for Actions Semi S500 Reset Management Unit
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*
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* Copyright (c) 2014 Actions Semi Inc.
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* Copyright (c) 2020 Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
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*/
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#ifndef __DT_BINDINGS_ACTIONS_S500_RESET_H
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#define __DT_BINDINGS_ACTIONS_S500_RESET_H
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#define RESET_DMAC 0
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#define RESET_NORIF 1
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#define RESET_DDR 2
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#define RESET_NANDC 3
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#define RESET_SD0 4
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#define RESET_SD1 5
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#define RESET_PCM1 6
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#define RESET_DE 7
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#define RESET_LCD 8
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#define RESET_SD2 9
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#define RESET_DSI 10
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#define RESET_CSI 11
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#define RESET_BISP 12
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#define RESET_KEY 13
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#define RESET_GPIO 14
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#define RESET_AUDIO 15
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#define RESET_PCM0 16
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#define RESET_VDE 17
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#define RESET_VCE 18
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#define RESET_GPU3D 19
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#define RESET_NIC301 20
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#define RESET_LENS 21
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#define RESET_PERIPHRESET 22
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#define RESET_USB2_0 23
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#define RESET_TVOUT 24
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#define RESET_HDMI 25
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#define RESET_HDCP2TX 26
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#define RESET_UART6 27
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#define RESET_UART0 28
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#define RESET_UART1 29
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#define RESET_UART2 30
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#define RESET_SPI0 31
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#define RESET_SPI1 32
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#define RESET_SPI2 33
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#define RESET_SPI3 34
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#define RESET_I2C0 35
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#define RESET_I2C1 36
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#define RESET_USB3 37
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#define RESET_UART3 38
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#define RESET_UART4 39
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#define RESET_UART5 40
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#define RESET_I2C2 41
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#define RESET_I2C3 42
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#define RESET_ETHERNET 43
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#define RESET_CHIPID 44
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#define RESET_USB2_1 45
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#define RESET_WD0RESET 46
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#define RESET_WD1RESET 47
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#define RESET_WD2RESET 48
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#define RESET_WD3RESET 49
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#define RESET_DBG0RESET 50
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#define RESET_DBG1RESET 51
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#define RESET_DBG2RESET 52
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#define RESET_DBG3RESET 53
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#endif /* __DT_BINDINGS_ACTIONS_S500_RESET_H */
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