1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
| /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
| #ifndef __DT_BINDINGS_POWER_RK3328_POWER_H__
| #define __DT_BINDINGS_POWER_RK3328_POWER_H__
|
| /**
| * RK3328 idle id Summary.
| */
| #define RK3328_PD_CORE 0
| #define RK3328_PD_GPU 1
| #define RK3328_PD_BUS 2
| #define RK3328_PD_MSCH 3
| #define RK3328_PD_PERI 4
| #define RK3328_PD_VIDEO 5
| #define RK3328_PD_HEVC 6
| #define RK3328_PD_SYS 7
| #define RK3328_PD_VPU 8
| #define RK3328_PD_VIO 9
|
| #endif
|
|
