/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef DT_BINDINGS_MEMORY_TEGRA30_MC_H
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#define DT_BINDINGS_MEMORY_TEGRA30_MC_H
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#define TEGRA_SWGROUP_PTC 0
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#define TEGRA_SWGROUP_DC 1
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#define TEGRA_SWGROUP_DCB 2
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#define TEGRA_SWGROUP_EPP 3
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#define TEGRA_SWGROUP_G2 4
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#define TEGRA_SWGROUP_MPE 5
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#define TEGRA_SWGROUP_VI 6
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#define TEGRA_SWGROUP_AFI 7
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#define TEGRA_SWGROUP_AVPC 8
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#define TEGRA_SWGROUP_NV 9
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#define TEGRA_SWGROUP_NV2 10
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#define TEGRA_SWGROUP_HDA 11
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#define TEGRA_SWGROUP_HC 12
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#define TEGRA_SWGROUP_PPCS 13
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#define TEGRA_SWGROUP_SATA 14
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#define TEGRA_SWGROUP_VDE 15
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#define TEGRA_SWGROUP_MPCORELP 16
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#define TEGRA_SWGROUP_MPCORE 17
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#define TEGRA_SWGROUP_ISP 18
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#define TEGRA30_MC_RESET_AFI 0
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#define TEGRA30_MC_RESET_AVPC 1
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#define TEGRA30_MC_RESET_DC 2
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#define TEGRA30_MC_RESET_DCB 3
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#define TEGRA30_MC_RESET_EPP 4
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#define TEGRA30_MC_RESET_2D 5
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#define TEGRA30_MC_RESET_HC 6
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#define TEGRA30_MC_RESET_HDA 7
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#define TEGRA30_MC_RESET_ISP 8
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#define TEGRA30_MC_RESET_MPCORE 9
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#define TEGRA30_MC_RESET_MPCORELP 10
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#define TEGRA30_MC_RESET_MPE 11
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#define TEGRA30_MC_RESET_3D 12
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#define TEGRA30_MC_RESET_3D2 13
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#define TEGRA30_MC_RESET_PPCS 14
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#define TEGRA30_MC_RESET_SATA 15
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#define TEGRA30_MC_RESET_VDE 16
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#define TEGRA30_MC_RESET_VI 17
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#endif
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