/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
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*/
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#ifndef _DT_BINDINGS_DRAM_ROCKCHIP_RV1126_H
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#define _DT_BINDINGS_DRAM_ROCKCHIP_RV1126_H
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#include <dt-bindings/memory/rockchip-dram.h>
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#define PHY_DDR3_RON_DISABLE (0x0)
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#define PHY_DDR3_RON_455ohm (0x1)
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#define PHY_DDR3_RON_230ohm (0x2)
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#define PHY_DDR3_RON_153ohm (0x3)
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#define PHY_DDR3_RON_115ohm (0x4)
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#define PHY_DDR3_RON_91ohm (0x5)
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#define PHY_DDR3_RON_76ohm (0x6)
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#define PHY_DDR3_RON_65ohm (0x7)
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#define PHY_DDR3_RON_57ohm (0x10)
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#define PHY_DDR3_RON_51ohm (0x11)
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#define PHY_DDR3_RON_46ohm (0x12)
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#define PHY_DDR3_RON_41ohm (0x13)
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#define PHY_DDR3_RON_38ohm (0x14)
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#define PHY_DDR3_RON_35ohm (0x15)
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#define PHY_DDR3_RON_32ohm (0x16)
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#define PHY_DDR3_RON_30ohm (0x17)
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#define PHY_DDR3_RON_28ohm (0x18)
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#define PHY_DDR3_RON_27ohm (0x19)
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#define PHY_DDR3_RON_25ohm (0x1a)
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#define PHY_DDR3_RON_24ohm (0x1b)
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#define PHY_DDR3_RON_23ohm (0x1c)
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#define PHY_DDR3_RON_22ohm (0x1d)
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#define PHY_DDR3_RON_21ohm (0x1e)
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#define PHY_DDR3_RON_20ohm (0x1f)
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#define PHY_DDR3_RTT_DISABLE (0x0)
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#define PHY_DDR3_RTT_561ohm (0x1)
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#define PHY_DDR3_RTT_282ohm (0x2)
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#define PHY_DDR3_RTT_188ohm (0x3)
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#define PHY_DDR3_RTT_141ohm (0x4)
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#define PHY_DDR3_RTT_113ohm (0x5)
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#define PHY_DDR3_RTT_94ohm (0x6)
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#define PHY_DDR3_RTT_81ohm (0x7)
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#define PHY_DDR3_RTT_72ohm (0x10)
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#define PHY_DDR3_RTT_64ohm (0x11)
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#define PHY_DDR3_RTT_58ohm (0x12)
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#define PHY_DDR3_RTT_52ohm (0x13)
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#define PHY_DDR3_RTT_48ohm (0x14)
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#define PHY_DDR3_RTT_44ohm (0x15)
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#define PHY_DDR3_RTT_41ohm (0x16)
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#define PHY_DDR3_RTT_38ohm (0x17)
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#define PHY_DDR3_RTT_37ohm (0x18)
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#define PHY_DDR3_RTT_34ohm (0x19)
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#define PHY_DDR3_RTT_32ohm (0x1a)
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#define PHY_DDR3_RTT_31ohm (0x1b)
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#define PHY_DDR3_RTT_29ohm (0x1c)
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#define PHY_DDR3_RTT_28ohm (0x1d)
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#define PHY_DDR3_RTT_27ohm (0x1e)
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#define PHY_DDR3_RTT_25ohm (0x1f)
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#define PHY_DDR4_LPDDR3_RON_DISABLE (0x0)
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#define PHY_DDR4_LPDDR3_RON_482ohm (0x1)
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#define PHY_DDR4_LPDDR3_RON_244ohm (0x2)
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#define PHY_DDR4_LPDDR3_RON_162ohm (0x3)
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#define PHY_DDR4_LPDDR3_RON_122ohm (0x4)
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#define PHY_DDR4_LPDDR3_RON_97ohm (0x5)
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#define PHY_DDR4_LPDDR3_RON_81ohm (0x6)
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#define PHY_DDR4_LPDDR3_RON_69ohm (0x7)
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#define PHY_DDR4_LPDDR3_RON_61ohm (0x10)
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#define PHY_DDR4_LPDDR3_RON_54ohm (0x11)
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#define PHY_DDR4_LPDDR3_RON_48ohm (0x12)
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#define PHY_DDR4_LPDDR3_RON_44ohm (0x13)
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#define PHY_DDR4_LPDDR3_RON_40ohm (0x14)
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#define PHY_DDR4_LPDDR3_RON_37ohm (0x15)
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#define PHY_DDR4_LPDDR3_RON_34ohm (0x16)
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#define PHY_DDR4_LPDDR3_RON_32ohm (0x17)
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#define PHY_DDR4_LPDDR3_RON_30ohm (0x18)
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#define PHY_DDR4_LPDDR3_RON_28ohm (0x19)
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#define PHY_DDR4_LPDDR3_RON_27ohm (0x1a)
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#define PHY_DDR4_LPDDR3_RON_25ohm (0x1b)
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#define PHY_DDR4_LPDDR3_RON_24ohm (0x1c)
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#define PHY_DDR4_LPDDR3_RON_23ohm (0x1d)
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#define PHY_DDR4_LPDDR3_RON_22ohm (0x1e)
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#define PHY_DDR4_LPDDR3_RON_21ohm (0x1f)
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#define PHY_DDR4_LPDDR3_RTT_DISABLE (0x0)
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#define PHY_DDR4_LPDDR3_RTT_586ohm (0x1)
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#define PHY_DDR4_LPDDR3_RTT_294ohm (0x2)
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#define PHY_DDR4_LPDDR3_RTT_196ohm (0x3)
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#define PHY_DDR4_LPDDR3_RTT_148ohm (0x4)
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#define PHY_DDR4_LPDDR3_RTT_118ohm (0x5)
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#define PHY_DDR4_LPDDR3_RTT_99ohm (0x6)
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#define PHY_DDR4_LPDDR3_RTT_85ohm (0x7)
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#define PHY_DDR4_LPDDR3_RTT_76ohm (0x10)
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#define PHY_DDR4_LPDDR3_RTT_67ohm (0x11)
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#define PHY_DDR4_LPDDR3_RTT_60ohm (0x12)
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#define PHY_DDR4_LPDDR3_RTT_55ohm (0x13)
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#define PHY_DDR4_LPDDR3_RTT_50ohm (0x14)
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#define PHY_DDR4_LPDDR3_RTT_46ohm (0x15)
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#define PHY_DDR4_LPDDR3_RTT_43ohm (0x16)
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#define PHY_DDR4_LPDDR3_RTT_40ohm (0x17)
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#define PHY_DDR4_LPDDR3_RTT_38ohm (0x18)
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#define PHY_DDR4_LPDDR3_RTT_36ohm (0x19)
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#define PHY_DDR4_LPDDR3_RTT_34ohm (0x1a)
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#define PHY_DDR4_LPDDR3_RTT_32ohm (0x1b)
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#define PHY_DDR4_LPDDR3_RTT_31ohm (0x1c)
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#define PHY_DDR4_LPDDR3_RTT_29ohm (0x1d)
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#define PHY_DDR4_LPDDR3_RTT_28ohm (0x1e)
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#define PHY_DDR4_LPDDR3_RTT_27ohm (0x1f)
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#define PHY_LPDDR4_RON_DISABLE (0x0)
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#define PHY_LPDDR4_RON_501ohm (0x1)
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#define PHY_LPDDR4_RON_253ohm (0x2)
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#define PHY_LPDDR4_RON_168ohm (0x3)
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#define PHY_LPDDR4_RON_126ohm (0x4)
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#define PHY_LPDDR4_RON_101ohm (0x5)
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#define PHY_LPDDR4_RON_84ohm (0x6)
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#define PHY_LPDDR4_RON_72ohm (0x7)
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#define PHY_LPDDR4_RON_63ohm (0x10)
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#define PHY_LPDDR4_RON_56ohm (0x11)
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#define PHY_LPDDR4_RON_50ohm (0x12)
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#define PHY_LPDDR4_RON_46ohm (0x13)
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#define PHY_LPDDR4_RON_42ohm (0x14)
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#define PHY_LPDDR4_RON_38ohm (0x15)
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#define PHY_LPDDR4_RON_36ohm (0x16)
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#define PHY_LPDDR4_RON_33ohm (0x17)
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#define PHY_LPDDR4_RON_31ohm (0x18)
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#define PHY_LPDDR4_RON_29ohm (0x19)
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#define PHY_LPDDR4_RON_28ohm (0x1a)
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#define PHY_LPDDR4_RON_26ohm (0x1b)
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#define PHY_LPDDR4_RON_25ohm (0x1c)
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#define PHY_LPDDR4_RON_24ohm (0x1d)
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#define PHY_LPDDR4_RON_23ohm (0x1e)
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#define PHY_LPDDR4_RON_22ohm (0x1f)
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#define PHY_LPDDR4_RTT_DISABLE (0x0)
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#define PHY_LPDDR4_RTT_604ohm (0x1)
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#define PHY_LPDDR4_RTT_303ohm (0x2)
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#define PHY_LPDDR4_RTT_202ohm (0x3)
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#define PHY_LPDDR4_RTT_152ohm (0x4)
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#define PHY_LPDDR4_RTT_122ohm (0x5)
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#define PHY_LPDDR4_RTT_101ohm (0x6)
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#define PHY_LPDDR4_RTT_87ohm (0x7)
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#define PHY_LPDDR4_RTT_78ohm (0x10)
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#define PHY_LPDDR4_RTT_69ohm (0x11)
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#define PHY_LPDDR4_RTT_62ohm (0x12)
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#define PHY_LPDDR4_RTT_56ohm (0x13)
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#define PHY_LPDDR4_RTT_52ohm (0x14)
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#define PHY_LPDDR4_RTT_48ohm (0x15)
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#define PHY_LPDDR4_RTT_44ohm (0x16)
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#define PHY_LPDDR4_RTT_41ohm (0x17)
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#define PHY_LPDDR4_RTT_39ohm (0x18)
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#define PHY_LPDDR4_RTT_37ohm (0x19)
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#define PHY_LPDDR4_RTT_35ohm (0x1a)
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#define PHY_LPDDR4_RTT_33ohm (0x1b)
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#define PHY_LPDDR4_RTT_32ohm (0x1c)
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#define PHY_LPDDR4_RTT_30ohm (0x1d)
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#define PHY_LPDDR4_RTT_29ohm (0x1e)
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#define PHY_LPDDR4_RTT_27ohm (0x1f)
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#endif /*_DT_BINDINGS_DRAM_ROCKCHIP_RV1126_H*/
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