/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2015 MediaTek Inc.
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* Author: Honghui Zhang <honghui.zhang@mediatek.com>
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*/
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#ifndef _DT_BINDINGS_MEMORY_MT2701_LARB_PORT_H_
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#define _DT_BINDINGS_MEMORY_MT2701_LARB_PORT_H_
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/*
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* Mediatek m4u generation 1 such as mt2701 has flat m4u port numbers,
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* the first port's id for larb[N] would be the last port's id of larb[N - 1]
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* plus one while larb[0]'s first port number is 0. The definition of
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* MT2701_M4U_ID_LARBx is following HW register spec.
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* But m4u generation 2 like mt8173 have different port number, it use fixed
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* offset for each larb, the first port's id for larb[N] would be (N * 32).
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*/
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#define LARB0_PORT_OFFSET 0
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#define LARB1_PORT_OFFSET 11
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#define LARB2_PORT_OFFSET 21
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#define LARB3_PORT_OFFSET 44
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#define MT2701_M4U_ID_LARB0(port) ((port) + LARB0_PORT_OFFSET)
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#define MT2701_M4U_ID_LARB1(port) ((port) + LARB1_PORT_OFFSET)
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#define MT2701_M4U_ID_LARB2(port) ((port) + LARB2_PORT_OFFSET)
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/* Port define for larb0 */
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#define MT2701_M4U_PORT_DISP_OVL_0 MT2701_M4U_ID_LARB0(0)
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#define MT2701_M4U_PORT_DISP_RDMA1 MT2701_M4U_ID_LARB0(1)
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#define MT2701_M4U_PORT_DISP_RDMA MT2701_M4U_ID_LARB0(2)
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#define MT2701_M4U_PORT_DISP_WDMA MT2701_M4U_ID_LARB0(3)
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#define MT2701_M4U_PORT_MM_CMDQ MT2701_M4U_ID_LARB0(4)
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#define MT2701_M4U_PORT_MDP_RDMA MT2701_M4U_ID_LARB0(5)
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#define MT2701_M4U_PORT_MDP_WDMA MT2701_M4U_ID_LARB0(6)
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#define MT2701_M4U_PORT_MDP_ROTO MT2701_M4U_ID_LARB0(7)
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#define MT2701_M4U_PORT_MDP_ROTCO MT2701_M4U_ID_LARB0(8)
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#define MT2701_M4U_PORT_MDP_ROTVO MT2701_M4U_ID_LARB0(9)
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#define MT2701_M4U_PORT_MDP_RDMA1 MT2701_M4U_ID_LARB0(10)
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/* Port define for larb1 */
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#define MT2701_M4U_PORT_VDEC_MC_EXT MT2701_M4U_ID_LARB1(0)
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#define MT2701_M4U_PORT_VDEC_PP_EXT MT2701_M4U_ID_LARB1(1)
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#define MT2701_M4U_PORT_VDEC_PPWRAP_EXT MT2701_M4U_ID_LARB1(2)
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#define MT2701_M4U_PORT_VDEC_AVC_MV_EXT MT2701_M4U_ID_LARB1(3)
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#define MT2701_M4U_PORT_VDEC_PRED_RD_EXT MT2701_M4U_ID_LARB1(4)
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#define MT2701_M4U_PORT_VDEC_PRED_WR_EXT MT2701_M4U_ID_LARB1(5)
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#define MT2701_M4U_PORT_VDEC_VLD_EXT MT2701_M4U_ID_LARB1(6)
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#define MT2701_M4U_PORT_VDEC_VLD2_EXT MT2701_M4U_ID_LARB1(7)
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#define MT2701_M4U_PORT_VDEC_TILE_EXT MT2701_M4U_ID_LARB1(8)
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#define MT2701_M4U_PORT_VDEC_IMG_RESZ_EXT MT2701_M4U_ID_LARB1(9)
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/* Port define for larb2 */
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#define MT2701_M4U_PORT_VENC_RCPU MT2701_M4U_ID_LARB2(0)
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#define MT2701_M4U_PORT_VENC_REC_FRM MT2701_M4U_ID_LARB2(1)
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#define MT2701_M4U_PORT_VENC_BSDMA MT2701_M4U_ID_LARB2(2)
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#define MT2701_M4U_PORT_JPGENC_RDMA MT2701_M4U_ID_LARB2(3)
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#define MT2701_M4U_PORT_VENC_LT_RCPU MT2701_M4U_ID_LARB2(4)
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#define MT2701_M4U_PORT_VENC_LT_REC_FRM MT2701_M4U_ID_LARB2(5)
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#define MT2701_M4U_PORT_VENC_LT_BSDMA MT2701_M4U_ID_LARB2(6)
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#define MT2701_M4U_PORT_JPGDEC_BSDMA MT2701_M4U_ID_LARB2(7)
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#define MT2701_M4U_PORT_VENC_SV_COMV MT2701_M4U_ID_LARB2(8)
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#define MT2701_M4U_PORT_VENC_RD_COMV MT2701_M4U_ID_LARB2(9)
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#define MT2701_M4U_PORT_JPGENC_BSDMA MT2701_M4U_ID_LARB2(10)
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#define MT2701_M4U_PORT_VENC_CUR_LUMA MT2701_M4U_ID_LARB2(11)
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#define MT2701_M4U_PORT_VENC_CUR_CHROMA MT2701_M4U_ID_LARB2(12)
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#define MT2701_M4U_PORT_VENC_REF_LUMA MT2701_M4U_ID_LARB2(13)
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#define MT2701_M4U_PORT_VENC_REF_CHROMA MT2701_M4U_ID_LARB2(14)
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#define MT2701_M4U_PORT_IMG_RESZ MT2701_M4U_ID_LARB2(15)
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#define MT2701_M4U_PORT_VENC_LT_SV_COMV MT2701_M4U_ID_LARB2(16)
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#define MT2701_M4U_PORT_VENC_LT_RD_COMV MT2701_M4U_ID_LARB2(17)
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#define MT2701_M4U_PORT_VENC_LT_CUR_LUMA MT2701_M4U_ID_LARB2(18)
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#define MT2701_M4U_PORT_VENC_LT_CUR_CHROMA MT2701_M4U_ID_LARB2(19)
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#define MT2701_M4U_PORT_VENC_LT_REF_LUMA MT2701_M4U_ID_LARB2(20)
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#define MT2701_M4U_PORT_VENC_LT_REF_CHROMA MT2701_M4U_ID_LARB2(21)
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#define MT2701_M4U_PORT_JPGDEC_WDMA MT2701_M4U_ID_LARB2(22)
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#endif
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