// SPDX-License-Identifier: GPL-2.0
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/*
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* Xilinx Video IP Core
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*
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* Copyright (C) 2013-2015 Ideas on Board
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* Copyright (C) 2013-2015 Xilinx, Inc.
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*
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* Contacts: Hyun Kwon <hyun.kwon@xilinx.com>
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* Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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*/
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#ifndef __DT_BINDINGS_MEDIA_XILINX_VIP_H__
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#define __DT_BINDINGS_MEDIA_XILINX_VIP_H__
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/*
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* Video format codes as defined in "AXI4-Stream Video IP and System Design
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* Guide".
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*/
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#define XVIP_VF_YUV_422 0
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#define XVIP_VF_YUV_444 1
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#define XVIP_VF_RBG 2
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#define XVIP_VF_YUV_420 3
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#define XVIP_VF_YUVA_422 4
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#define XVIP_VF_YUVA_444 5
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#define XVIP_VF_RGBA 6
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#define XVIP_VF_YUVA_420 7
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#define XVIP_VF_YUVD_422 8
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#define XVIP_VF_YUVD_444 9
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#define XVIP_VF_RGBD 10
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#define XVIP_VF_YUVD_420 11
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#define XVIP_VF_MONO_SENSOR 12
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#define XVIP_VF_CUSTOM2 13
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#define XVIP_VF_CUSTOM3 14
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#define XVIP_VF_CUSTOM4 15
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#endif /* __DT_BINDINGS_MEDIA_XILINX_VIP_H__ */
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