/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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* Author: Bibby Hsieh <bibby.hsieh@mediatek.com>
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*
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*/
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#ifndef _DT_BINDINGS_GCE_MT8183_H
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#define _DT_BINDINGS_GCE_MT8183_H
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#define CMDQ_NO_TIMEOUT 0xffffffff
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/* GCE HW thread priority */
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#define CMDQ_THR_PRIO_LOWEST 0
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#define CMDQ_THR_PRIO_HIGHEST 1
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/* GCE SUBSYS */
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#define SUBSYS_1300XXXX 0
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#define SUBSYS_1400XXXX 1
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#define SUBSYS_1401XXXX 2
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#define SUBSYS_1402XXXX 3
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#define SUBSYS_1502XXXX 4
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#define SUBSYS_1880XXXX 5
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#define SUBSYS_1881XXXX 6
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#define SUBSYS_1882XXXX 7
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#define SUBSYS_1883XXXX 8
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#define SUBSYS_1884XXXX 9
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#define SUBSYS_1000XXXX 10
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#define SUBSYS_1001XXXX 11
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#define SUBSYS_1002XXXX 12
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#define SUBSYS_1003XXXX 13
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#define SUBSYS_1004XXXX 14
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#define SUBSYS_1005XXXX 15
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#define SUBSYS_1020XXXX 16
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#define SUBSYS_1028XXXX 17
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#define SUBSYS_1700XXXX 18
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#define SUBSYS_1701XXXX 19
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#define SUBSYS_1702XXXX 20
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#define SUBSYS_1703XXXX 21
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#define SUBSYS_1800XXXX 22
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#define SUBSYS_1801XXXX 23
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#define SUBSYS_1802XXXX 24
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#define SUBSYS_1804XXXX 25
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#define SUBSYS_1805XXXX 26
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#define SUBSYS_1808XXXX 27
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#define SUBSYS_180aXXXX 28
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#define SUBSYS_180bXXXX 29
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#define CMDQ_EVENT_DISP_RDMA0_SOF 0
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#define CMDQ_EVENT_DISP_RDMA1_SOF 1
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#define CMDQ_EVENT_MDP_RDMA0_SOF 2
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#define CMDQ_EVENT_MDP_RSZ0_SOF 4
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#define CMDQ_EVENT_MDP_RSZ1_SOF 5
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#define CMDQ_EVENT_MDP_TDSHP_SOF 6
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#define CMDQ_EVENT_MDP_WROT0_SOF 7
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#define CMDQ_EVENT_MDP_WDMA0_SOF 8
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#define CMDQ_EVENT_DISP_OVL0_SOF 9
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#define CMDQ_EVENT_DISP_OVL0_2L_SOF 10
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#define CMDQ_EVENT_DISP_OVL1_2L_SOF 11
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#define CMDQ_EVENT_DISP_WDMA0_SOF 12
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#define CMDQ_EVENT_DISP_COLOR0_SOF 13
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#define CMDQ_EVENT_DISP_CCORR0_SOF 14
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#define CMDQ_EVENT_DISP_AAL0_SOF 15
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#define CMDQ_EVENT_DISP_GAMMA0_SOF 16
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#define CMDQ_EVENT_DISP_DITHER0_SOF 17
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#define CMDQ_EVENT_DISP_PWM0_SOF 18
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#define CMDQ_EVENT_DISP_DSI0_SOF 19
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#define CMDQ_EVENT_DISP_DPI0_SOF 20
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#define CMDQ_EVENT_DISP_RSZ_SOF 22
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#define CMDQ_EVENT_MDP_AAL_SOF 23
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#define CMDQ_EVENT_MDP_CCORR_SOF 24
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#define CMDQ_EVENT_DISP_DBI_SOF 25
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#define CMDQ_EVENT_DISP_RDMA0_EOF 26
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#define CMDQ_EVENT_DISP_RDMA1_EOF 27
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#define CMDQ_EVENT_MDP_RDMA0_EOF 28
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#define CMDQ_EVENT_MDP_RSZ0_EOF 30
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#define CMDQ_EVENT_MDP_RSZ1_EOF 31
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#define CMDQ_EVENT_MDP_TDSHP_EOF 32
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#define CMDQ_EVENT_MDP_WROT0_EOF 33
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#define CMDQ_EVENT_MDP_WDMA0_EOF 34
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#define CMDQ_EVENT_DISP_OVL0_EOF 35
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#define CMDQ_EVENT_DISP_OVL0_2L_EOF 36
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#define CMDQ_EVENT_DISP_OVL1_2L_EOF 37
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#define CMDQ_EVENT_DISP_WDMA0_EOF 38
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#define CMDQ_EVENT_DISP_COLOR0_EOF 39
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#define CMDQ_EVENT_DISP_CCORR0_EOF 40
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#define CMDQ_EVENT_DISP_AAL0_EOF 41
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#define CMDQ_EVENT_DISP_GAMMA0_EOF 42
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#define CMDQ_EVENT_DISP_DITHER0_EOF 43
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#define CMDQ_EVENT_DSI0_EOF 44
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#define CMDQ_EVENT_DPI0_EOF 45
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#define CMDQ_EVENT_DISP_RSZ_EOF 47
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#define CMDQ_EVENT_MDP_AAL_EOF 48
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#define CMDQ_EVENT_MDP_CCORR_EOF 49
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#define CMDQ_EVENT_DBI_EOF 50
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#define CMDQ_EVENT_MUTEX_STREAM_DONE0 130
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#define CMDQ_EVENT_MUTEX_STREAM_DONE1 131
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#define CMDQ_EVENT_MUTEX_STREAM_DONE2 132
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#define CMDQ_EVENT_MUTEX_STREAM_DONE3 133
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#define CMDQ_EVENT_MUTEX_STREAM_DONE4 134
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#define CMDQ_EVENT_MUTEX_STREAM_DONE5 135
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#define CMDQ_EVENT_MUTEX_STREAM_DONE6 136
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#define CMDQ_EVENT_MUTEX_STREAM_DONE7 137
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#define CMDQ_EVENT_MUTEX_STREAM_DONE8 138
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#define CMDQ_EVENT_MUTEX_STREAM_DONE9 139
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#define CMDQ_EVENT_MUTEX_STREAM_DONE10 140
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#define CMDQ_EVENT_MUTEX_STREAM_DONE11 141
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#define CMDQ_EVENT_DISP_RDMA0_BUF_UNDERRUN_EVEN 142
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#define CMDQ_EVENT_DISP_RDMA1_BUF_UNDERRUN_EVEN 143
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#define CMDQ_EVENT_DSI0_TE_EVENT 144
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#define CMDQ_EVENT_DSI0_IRQ_EVENT 145
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#define CMDQ_EVENT_DSI0_DONE_EVENT 146
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#define CMDQ_EVENT_DISP_WDMA0_SW_RST_DONE 150
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#define CMDQ_EVENT_MDP_WDMA_SW_RST_DONE 151
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#define CMDQ_EVENT_MDP_WROT0_SW_RST_DONE 152
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#define CMDQ_EVENT_MDP_RDMA0_SW_RST_DONE 154
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#define CMDQ_EVENT_DISP_OVL0_FRAME_RST_DONE_PULE 155
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#define CMDQ_EVENT_DISP_OVL0_2L_FRAME_RST_DONE_ULSE 156
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#define CMDQ_EVENT_DISP_OVL1_2L_FRAME_RST_DONE_ULSE 157
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#define CMDQ_EVENT_ISP_FRAME_DONE_P2_0 257
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#define CMDQ_EVENT_ISP_FRAME_DONE_P2_1 258
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#define CMDQ_EVENT_ISP_FRAME_DONE_P2_2 259
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#define CMDQ_EVENT_ISP_FRAME_DONE_P2_3 260
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#define CMDQ_EVENT_ISP_FRAME_DONE_P2_4 261
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#define CMDQ_EVENT_ISP_FRAME_DONE_P2_5 262
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#define CMDQ_EVENT_ISP_FRAME_DONE_P2_6 263
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#define CMDQ_EVENT_ISP_FRAME_DONE_P2_7 264
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#define CMDQ_EVENT_ISP_FRAME_DONE_P2_8 265
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#define CMDQ_EVENT_ISP_FRAME_DONE_P2_9 266
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#define CMDQ_EVENT_ISP_FRAME_DONE_P2_10 267
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#define CMDQ_EVENT_ISP_FRAME_DONE_P2_11 268
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#define CMDQ_EVENT_ISP_FRAME_DONE_P2_12 269
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#define CMDQ_EVENT_ISP_FRAME_DONE_P2_13 270
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#define CMDQ_EVENT_ISP_FRAME_DONE_P2_14 271
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#define CMDQ_EVENT_ISP_FRAME_DONE_P2_15 272
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#define CMDQ_EVENT_ISP_FRAME_DONE_P2_16 273
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#define CMDQ_EVENT_ISP_FRAME_DONE_P2_17 274
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#define CMDQ_EVENT_ISP_FRAME_DONE_P2_18 275
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#define CMDQ_EVENT_AMD_FRAME_DONE 276
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#define CMDQ_EVENT_DVE_DONE 277
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#define CMDQ_EVENT_WMFE_DONE 278
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#define CMDQ_EVENT_RSC_DONE 279
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#define CMDQ_EVENT_MFB_DONE 280
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#define CMDQ_EVENT_WPE_A_DONE 281
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#define CMDQ_EVENT_SPE_B_DONE 282
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#define CMDQ_EVENT_OCC_DONE 283
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#define CMDQ_EVENT_VENC_CMDQ_FRAME_DONE 289
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#define CMDQ_EVENT_JPG_ENC_CMDQ_DONE 290
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#define CMDQ_EVENT_JPG_DEC_CMDQ_DONE 291
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#define CMDQ_EVENT_VENC_CMDQ_MB_DONE 292
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#define CMDQ_EVENT_VENC_CMDQ_128BYTE_DONE 293
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#define CMDQ_EVENT_ISP_FRAME_DONE_A 321
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#define CMDQ_EVENT_ISP_FRAME_DONE_B 322
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#define CMDQ_EVENT_CAMSV0_PASS1_DONE 323
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#define CMDQ_EVENT_CAMSV1_PASS1_DONE 324
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#define CMDQ_EVENT_CAMSV2_PASS1_DONE 325
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#define CMDQ_EVENT_TSF_DONE 326
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#define CMDQ_EVENT_SENINF_CAM0_FIFO_FULL 327
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#define CMDQ_EVENT_SENINF_CAM1_FIFO_FULL 328
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#define CMDQ_EVENT_SENINF_CAM2_FIFO_FULL 329
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#define CMDQ_EVENT_SENINF_CAM3_FIFO_FULL 330
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#define CMDQ_EVENT_SENINF_CAM4_FIFO_FULL 331
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#define CMDQ_EVENT_SENINF_CAM5_FIFO_FULL 332
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#define CMDQ_EVENT_SENINF_CAM6_FIFO_FULL 333
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#define CMDQ_EVENT_SENINF_CAM7_FIFO_FULL 334
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#define CMDQ_EVENT_IPU_CORE0_DONE0 353
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#define CMDQ_EVENT_IPU_CORE0_DONE1 354
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#define CMDQ_EVENT_IPU_CORE0_DONE2 355
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#define CMDQ_EVENT_IPU_CORE0_DONE3 356
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#define CMDQ_EVENT_IPU_CORE1_DONE0 385
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#define CMDQ_EVENT_IPU_CORE1_DONE1 386
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#define CMDQ_EVENT_IPU_CORE1_DONE2 387
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#define CMDQ_EVENT_IPU_CORE1_DONE3 388
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#endif
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