/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2018 MediaTek Inc.
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* Author: Houlong Wei <houlong.wei@mediatek.com>
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*
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*/
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#ifndef _DT_BINDINGS_GCE_MT8173_H
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#define _DT_BINDINGS_GCE_MT8173_H
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/* GCE HW thread priority */
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#define CMDQ_THR_PRIO_LOWEST 0
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#define CMDQ_THR_PRIO_HIGHEST 1
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/* GCE SUBSYS */
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#define SUBSYS_1400XXXX 1
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#define SUBSYS_1401XXXX 2
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#define SUBSYS_1402XXXX 3
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/* GCE HW EVENT */
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#define CMDQ_EVENT_DISP_OVL0_SOF 11
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#define CMDQ_EVENT_DISP_OVL1_SOF 12
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#define CMDQ_EVENT_DISP_RDMA0_SOF 13
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#define CMDQ_EVENT_DISP_RDMA1_SOF 14
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#define CMDQ_EVENT_DISP_RDMA2_SOF 15
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#define CMDQ_EVENT_DISP_WDMA0_SOF 16
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#define CMDQ_EVENT_DISP_WDMA1_SOF 17
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#define CMDQ_EVENT_DISP_OVL0_EOF 39
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#define CMDQ_EVENT_DISP_OVL1_EOF 40
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#define CMDQ_EVENT_DISP_RDMA0_EOF 41
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#define CMDQ_EVENT_DISP_RDMA1_EOF 42
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#define CMDQ_EVENT_DISP_RDMA2_EOF 43
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#define CMDQ_EVENT_DISP_WDMA0_EOF 44
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#define CMDQ_EVENT_DISP_WDMA1_EOF 45
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#define CMDQ_EVENT_MUTEX0_STREAM_EOF 53
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#define CMDQ_EVENT_MUTEX1_STREAM_EOF 54
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#define CMDQ_EVENT_MUTEX2_STREAM_EOF 55
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#define CMDQ_EVENT_MUTEX3_STREAM_EOF 56
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#define CMDQ_EVENT_MUTEX4_STREAM_EOF 57
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#define CMDQ_EVENT_DISP_RDMA0_UNDERRUN 63
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#define CMDQ_EVENT_DISP_RDMA1_UNDERRUN 64
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#define CMDQ_EVENT_DISP_RDMA2_UNDERRUN 65
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#endif
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