#ifndef __DT_BINDINGS_DMA_JZ4780_DMA_H__
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#define __DT_BINDINGS_DMA_JZ4780_DMA_H__
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/*
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* Request type numbers for the JZ4780 DMA controller (written to the DRTn
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* register for the channel).
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*/
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#define JZ4780_DMA_I2S1_TX 0x4
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#define JZ4780_DMA_I2S1_RX 0x5
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#define JZ4780_DMA_I2S0_TX 0x6
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#define JZ4780_DMA_I2S0_RX 0x7
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#define JZ4780_DMA_AUTO 0x8
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#define JZ4780_DMA_SADC_RX 0x9
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#define JZ4780_DMA_UART4_TX 0xc
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#define JZ4780_DMA_UART4_RX 0xd
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#define JZ4780_DMA_UART3_TX 0xe
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#define JZ4780_DMA_UART3_RX 0xf
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#define JZ4780_DMA_UART2_TX 0x10
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#define JZ4780_DMA_UART2_RX 0x11
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#define JZ4780_DMA_UART1_TX 0x12
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#define JZ4780_DMA_UART1_RX 0x13
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#define JZ4780_DMA_UART0_TX 0x14
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#define JZ4780_DMA_UART0_RX 0x15
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#define JZ4780_DMA_SSI0_TX 0x16
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#define JZ4780_DMA_SSI0_RX 0x17
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#define JZ4780_DMA_SSI1_TX 0x18
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#define JZ4780_DMA_SSI1_RX 0x19
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#define JZ4780_DMA_MSC0_TX 0x1a
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#define JZ4780_DMA_MSC0_RX 0x1b
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#define JZ4780_DMA_MSC1_TX 0x1c
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#define JZ4780_DMA_MSC1_RX 0x1d
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#define JZ4780_DMA_MSC2_TX 0x1e
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#define JZ4780_DMA_MSC2_RX 0x1f
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#define JZ4780_DMA_PCM0_TX 0x20
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#define JZ4780_DMA_PCM0_RX 0x21
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#define JZ4780_DMA_SMB0_TX 0x24
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#define JZ4780_DMA_SMB0_RX 0x25
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#define JZ4780_DMA_SMB1_TX 0x26
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#define JZ4780_DMA_SMB1_RX 0x27
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#define JZ4780_DMA_SMB2_TX 0x28
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#define JZ4780_DMA_SMB2_RX 0x29
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#define JZ4780_DMA_SMB3_TX 0x2a
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#define JZ4780_DMA_SMB3_RX 0x2b
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#define JZ4780_DMA_SMB4_TX 0x2c
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#define JZ4780_DMA_SMB4_RX 0x2d
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#define JZ4780_DMA_DES_TX 0x2e
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#define JZ4780_DMA_DES_RX 0x2f
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#endif /* __DT_BINDINGS_DMA_JZ4780_DMA_H__ */
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