/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2015 - 2016 ZTE Corporation.
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*/
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#ifndef __DT_BINDINGS_CLOCK_ZX296718_H
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#define __DT_BINDINGS_CLOCK_ZX296718_H
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/* PLL */
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#define ZX296718_PLL_CPU 1
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#define ZX296718_PLL_MAC 2
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#define ZX296718_PLL_MM0 3
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#define ZX296718_PLL_MM1 4
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#define ZX296718_PLL_VGA 5
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#define ZX296718_PLL_DDR 6
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#define ZX296718_PLL_AUDIO 7
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#define ZX296718_PLL_HSIC 8
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#define CPU_DBG_GATE 9
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#define A72_GATE 10
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#define CPU_PERI_GATE 11
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#define A53_GATE 12
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#define DDR1_GATE 13
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#define DDR0_GATE 14
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#define SD1_WCLK 15
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#define SD1_AHB 16
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#define SD0_WCLK 17
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#define SD0_AHB 18
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#define EMMC_WCLK 19
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#define EMMC_NAND_AXI 20
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#define NAND_WCLK 21
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#define EMMC_NAND_AHB 22
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#define LSP1_148M5 23
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#define LSP1_99M 24
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#define LSP1_24M 25
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#define LSP0_74M25 26
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#define LSP0_32K 27
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#define LSP0_148M5 28
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#define LSP0_99M 29
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#define LSP0_24M 30
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#define DEMUX_AXI 31
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#define DEMUX_APB 32
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#define DEMUX_148M5 33
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#define DEMUX_108M 34
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#define AUDIO_APB 35
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#define AUDIO_99M 36
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#define AUDIO_24M 37
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#define AUDIO_16M384 38
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#define AUDIO_32K 39
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#define WDT_WCLK 40
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#define TIMER_WCLK 41
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#define VDE_ACLK 42
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#define VCE_ACLK 43
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#define HDE_ACLK 44
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#define GPU_ACLK 45
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#define SAPPU_ACLK 46
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#define SAPPU_WCLK 47
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#define VOU_ACLK 48
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#define VOU_MAIN_WCLK 49
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#define VOU_AUX_WCLK 50
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#define VOU_PPU_WCLK 51
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#define MIPI_CFG_CLK 52
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#define VGA_I2C_WCLK 53
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#define MIPI_REF_CLK 54
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#define HDMI_OSC_CEC 55
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#define HDMI_OSC_CLK 56
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#define HDMI_XCLK 57
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#define VIU_M0_ACLK 58
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#define VIU_M1_ACLK 59
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#define VIU_WCLK 60
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#define VIU_JPEG_WCLK 61
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#define VIU_CFG_CLK 62
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#define TS_SYS_WCLK 63
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#define TS_SYS_108M 64
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#define USB20_HCLK 65
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#define USB20_PHY_CLK 66
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#define USB21_HCLK 67
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#define USB21_PHY_CLK 68
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#define GMAC_RMIICLK 69
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#define GMAC_PCLK 70
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#define GMAC_ACLK 71
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#define GMAC_RFCLK 72
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#define TEMPSENSOR_GATE 73
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#define TOP_NR_CLKS 74
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#define LSP0_TIMER3_PCLK 1
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#define LSP0_TIMER3_WCLK 2
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#define LSP0_TIMER4_PCLK 3
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#define LSP0_TIMER4_WCLK 4
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#define LSP0_TIMER5_PCLK 5
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#define LSP0_TIMER5_WCLK 6
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#define LSP0_UART3_PCLK 7
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#define LSP0_UART3_WCLK 8
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#define LSP0_UART1_PCLK 9
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#define LSP0_UART1_WCLK 10
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#define LSP0_UART2_PCLK 11
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#define LSP0_UART2_WCLK 12
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#define LSP0_SPIFC0_PCLK 13
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#define LSP0_SPIFC0_WCLK 14
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#define LSP0_I2C4_PCLK 15
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#define LSP0_I2C4_WCLK 16
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#define LSP0_I2C5_PCLK 17
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#define LSP0_I2C5_WCLK 18
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#define LSP0_SSP0_PCLK 19
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#define LSP0_SSP0_WCLK 20
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#define LSP0_SSP1_PCLK 21
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#define LSP0_SSP1_WCLK 22
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#define LSP0_USIM_PCLK 23
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#define LSP0_USIM_WCLK 24
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#define LSP0_GPIO_PCLK 25
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#define LSP0_GPIO_WCLK 26
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#define LSP0_I2C3_PCLK 27
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#define LSP0_I2C3_WCLK 28
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#define LSP0_NR_CLKS 29
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#define LSP1_UART4_PCLK 1
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#define LSP1_UART4_WCLK 2
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#define LSP1_UART5_PCLK 3
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#define LSP1_UART5_WCLK 4
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#define LSP1_PWM_PCLK 5
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#define LSP1_PWM_WCLK 6
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#define LSP1_I2C2_PCLK 7
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#define LSP1_I2C2_WCLK 8
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#define LSP1_SSP2_PCLK 9
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#define LSP1_SSP2_WCLK 10
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#define LSP1_SSP3_PCLK 11
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#define LSP1_SSP3_WCLK 12
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#define LSP1_SSP4_PCLK 13
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#define LSP1_SSP4_WCLK 14
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#define LSP1_USIM1_PCLK 15
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#define LSP1_USIM1_WCLK 16
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#define LSP1_NR_CLKS 17
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#define AUDIO_I2S0_WCLK 1
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#define AUDIO_I2S0_PCLK 2
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#define AUDIO_I2S1_WCLK 3
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#define AUDIO_I2S1_PCLK 4
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#define AUDIO_I2S2_WCLK 5
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#define AUDIO_I2S2_PCLK 6
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#define AUDIO_I2S3_WCLK 7
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#define AUDIO_I2S3_PCLK 8
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#define AUDIO_I2C0_WCLK 9
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#define AUDIO_I2C0_PCLK 10
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#define AUDIO_SPDIF0_WCLK 11
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#define AUDIO_SPDIF0_PCLK 12
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#define AUDIO_SPDIF1_WCLK 13
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#define AUDIO_SPDIF1_PCLK 14
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#define AUDIO_TIMER_WCLK 15
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#define AUDIO_TIMER_PCLK 16
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#define AUDIO_TDM_WCLK 17
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#define AUDIO_TDM_PCLK 18
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#define AUDIO_TS_PCLK 19
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#define I2S0_WCLK_MUX 20
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#define I2S1_WCLK_MUX 21
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#define I2S2_WCLK_MUX 22
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#define I2S3_WCLK_MUX 23
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#define AUDIO_NR_CLKS 24
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#endif
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