/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
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/*
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* Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com>
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*/
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#ifndef _DT_BINDINGS_CLK_SUN50I_A100_H_
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#define _DT_BINDINGS_CLK_SUN50I_A100_H_
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#define CLK_PLL_PERIPH0 3
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#define CLK_CPUX 24
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#define CLK_APB1 29
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#define CLK_MBUS 31
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#define CLK_DE 32
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#define CLK_BUS_DE 33
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#define CLK_G2D 34
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#define CLK_BUS_G2D 35
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#define CLK_GPU 36
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#define CLK_BUS_GPU 37
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#define CLK_CE 38
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#define CLK_BUS_CE 39
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#define CLK_VE 40
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#define CLK_BUS_VE 41
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#define CLK_BUS_DMA 42
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#define CLK_BUS_MSGBOX 43
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#define CLK_BUS_SPINLOCK 44
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#define CLK_BUS_HSTIMER 45
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#define CLK_AVS 46
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#define CLK_BUS_DBG 47
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#define CLK_BUS_PSI 48
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#define CLK_BUS_PWM 49
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#define CLK_BUS_IOMMU 50
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#define CLK_MBUS_DMA 51
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#define CLK_MBUS_VE 52
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#define CLK_MBUS_CE 53
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#define CLK_MBUS_NAND 54
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#define CLK_MBUS_CSI 55
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#define CLK_MBUS_ISP 56
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#define CLK_MBUS_G2D 57
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#define CLK_NAND0 59
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#define CLK_NAND1 60
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#define CLK_BUS_NAND 61
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#define CLK_MMC0 62
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#define CLK_MMC1 63
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#define CLK_MMC2 64
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#define CLK_MMC3 65
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#define CLK_BUS_MMC0 66
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#define CLK_BUS_MMC1 67
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#define CLK_BUS_MMC2 68
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#define CLK_BUS_UART0 69
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#define CLK_BUS_UART1 70
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#define CLK_BUS_UART2 71
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#define CLK_BUS_UART3 72
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#define CLK_BUS_UART4 73
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#define CLK_BUS_I2C0 74
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#define CLK_BUS_I2C1 75
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#define CLK_BUS_I2C2 76
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#define CLK_BUS_I2C3 77
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#define CLK_SPI0 78
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#define CLK_SPI1 79
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#define CLK_SPI2 80
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#define CLK_BUS_SPI0 81
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#define CLK_BUS_SPI1 82
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#define CLK_BUS_SPI2 83
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#define CLK_EMAC_25M 84
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#define CLK_BUS_EMAC 85
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#define CLK_IR_RX 86
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#define CLK_BUS_IR_RX 87
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#define CLK_IR_TX 88
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#define CLK_BUS_IR_TX 89
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#define CLK_BUS_GPADC 90
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#define CLK_BUS_THS 91
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#define CLK_I2S0 92
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#define CLK_I2S1 93
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#define CLK_I2S2 94
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#define CLK_I2S3 95
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#define CLK_BUS_I2S0 96
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#define CLK_BUS_I2S1 97
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#define CLK_BUS_I2S2 98
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#define CLK_BUS_I2S3 99
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#define CLK_SPDIF 100
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#define CLK_BUS_SPDIF 101
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#define CLK_DMIC 102
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#define CLK_BUS_DMIC 103
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#define CLK_AUDIO_DAC 104
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#define CLK_AUDIO_ADC 105
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#define CLK_AUDIO_4X 106
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#define CLK_BUS_AUDIO_CODEC 107
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#define CLK_USB_OHCI0 108
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#define CLK_USB_PHY0 109
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#define CLK_USB_OHCI1 110
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#define CLK_USB_PHY1 111
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#define CLK_BUS_OHCI0 112
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#define CLK_BUS_OHCI1 113
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#define CLK_BUS_EHCI0 114
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#define CLK_BUS_EHCI1 115
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#define CLK_BUS_OTG 116
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#define CLK_BUS_LRADC 117
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#define CLK_BUS_DPSS_TOP0 118
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#define CLK_BUS_DPSS_TOP1 119
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#define CLK_MIPI_DSI 120
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#define CLK_BUS_MIPI_DSI 121
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#define CLK_TCON_LCD 122
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#define CLK_BUS_TCON_LCD 123
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#define CLK_LEDC 124
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#define CLK_BUS_LEDC 125
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#define CLK_CSI_TOP 126
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#define CLK_CSI0_MCLK 127
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#define CLK_CSI1_MCLK 128
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#define CLK_BUS_CSI 129
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#define CLK_CSI_ISP 130
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#endif /* _DT_BINDINGS_CLK_SUN50I_A100_H_ */
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