/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2015 Rockchip Electronics Co. Ltd.
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* Author: Xing Zheng <zhengxing@rock-chips.com>
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*/
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#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H
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#define _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H
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/* core clocks */
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#define PLL_APLL 1
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#define PLL_DPLL 2
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#define PLL_GPLL 3
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#define ARMCLK 4
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/* sclk gates (special clocks) */
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#define SCLK_GPU 64
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#define SCLK_SPI 65
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#define SCLK_SDMMC 68
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#define SCLK_SDIO 69
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#define SCLK_EMMC 71
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#define SCLK_NANDC 76
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#define SCLK_UART0 77
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#define SCLK_UART1 78
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#define SCLK_UART2 79
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#define SCLK_I2S 82
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#define SCLK_SPDIF 83
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#define SCLK_TIMER0 85
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#define SCLK_TIMER1 86
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#define SCLK_TIMER2 87
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#define SCLK_TIMER3 88
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#define SCLK_OTGPHY0 93
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#define SCLK_LCDC 100
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#define SCLK_HDMI 109
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#define SCLK_HEVC 111
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#define SCLK_I2S_OUT 113
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#define SCLK_SDMMC_DRV 114
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#define SCLK_SDIO_DRV 115
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#define SCLK_EMMC_DRV 117
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#define SCLK_SDMMC_SAMPLE 118
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#define SCLK_SDIO_SAMPLE 119
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#define SCLK_EMMC_SAMPLE 121
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#define SCLK_PVTM_CORE 123
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#define SCLK_PVTM_GPU 124
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#define SCLK_PVTM_VIDEO 125
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#define SCLK_I2S_FRAC 126
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#define SCLK_I2S_PRE 127
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#define SCLK_MAC 151
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#define SCLK_MACREF 152
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#define SCLK_MACPLL 153
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#define SCLK_SFC 160
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/* aclk gates */
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#define ACLK_DMAC2 194
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#define ACLK_LCDC 197
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#define ACLK_VIO 203
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#define ACLK_VCODEC 208
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#define ACLK_CPU 209
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#define ACLK_PERI 210
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#define ACLK_HEVC 211
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/* pclk gates */
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#define PCLK_GPIO0 320
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#define PCLK_GPIO1 321
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#define PCLK_GPIO2 322
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#define PCLK_GRF 329
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#define PCLK_I2C0 332
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#define PCLK_I2C1 333
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#define PCLK_I2C2 334
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#define PCLK_SPI 338
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#define PCLK_UART0 341
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#define PCLK_UART1 342
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#define PCLK_UART2 343
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#define PCLK_PWM 350
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#define PCLK_TIMER 353
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#define PCLK_HDMI 360
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#define PCLK_CPU 362
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#define PCLK_PERI 363
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#define PCLK_DDRUPCTL 364
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#define PCLK_WDT 368
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#define PCLK_ACODEC 369
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/* hclk gates */
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#define HCLK_OTG0 449
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#define HCLK_OTG1 450
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#define HCLK_NANDC 453
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#define HCLK_SFC 454
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#define HCLK_SDMMC 456
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#define HCLK_SDIO 457
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#define HCLK_EMMC 459
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#define HCLK_MAC 460
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#define HCLK_I2S 462
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#define HCLK_LCDC 465
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#define HCLK_ROM 467
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#define HCLK_VIO_BUS 472
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#define HCLK_VCODEC 476
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#define HCLK_CPU 477
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#define HCLK_PERI 478
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#define CLK_NR_CLKS (HCLK_PERI + 1)
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/* soft-reset indices */
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#define SRST_CORE0 0
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#define SRST_CORE1 1
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#define SRST_CORE0_DBG 4
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#define SRST_CORE1_DBG 5
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#define SRST_CORE0_POR 8
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#define SRST_CORE1_POR 9
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#define SRST_L2C 12
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#define SRST_TOPDBG 13
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#define SRST_STRC_SYS_A 14
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#define SRST_PD_CORE_NIU 15
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#define SRST_TIMER2 16
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#define SRST_CPUSYS_H 17
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#define SRST_AHB2APB_H 19
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#define SRST_TIMER3 20
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#define SRST_INTMEM 21
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#define SRST_ROM 22
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#define SRST_PERI_NIU 23
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#define SRST_I2S 24
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#define SRST_DDR_PLL 25
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#define SRST_GPU_DLL 26
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#define SRST_TIMER0 27
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#define SRST_TIMER1 28
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#define SRST_CORE_DLL 29
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#define SRST_EFUSE_P 30
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#define SRST_ACODEC_P 31
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#define SRST_GPIO0 32
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#define SRST_GPIO1 33
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#define SRST_GPIO2 34
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#define SRST_UART0 39
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#define SRST_UART1 40
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#define SRST_UART2 41
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#define SRST_I2C0 43
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#define SRST_I2C1 44
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#define SRST_I2C2 45
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#define SRST_SFC 47
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#define SRST_PWM0 48
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#define SRST_DAP 51
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#define SRST_DAP_SYS 52
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#define SRST_GRF 55
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#define SRST_PERIPHSYS_A 57
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#define SRST_PERIPHSYS_H 58
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#define SRST_PERIPHSYS_P 59
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#define SRST_CPU_PERI 61
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#define SRST_EMEM_PERI 62
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#define SRST_USB_PERI 63
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#define SRST_DMA2 64
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#define SRST_MAC 66
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#define SRST_NANDC 68
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#define SRST_USBOTG0 69
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#define SRST_OTGC0 71
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#define SRST_USBOTG1 72
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#define SRST_OTGC1 74
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#define SRST_DDRMSCH 79
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#define SRST_MMC0 81
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#define SRST_SDIO 82
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#define SRST_EMMC 83
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#define SRST_SPI0 84
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#define SRST_WDT 86
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#define SRST_DDRPHY 88
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#define SRST_DDRPHY_P 89
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#define SRST_DDRCTRL 90
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#define SRST_DDRCTRL_P 91
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#define SRST_HDMI_P 96
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#define SRST_VIO_BUS_H 99
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#define SRST_UTMI0 103
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#define SRST_UTMI1 104
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#define SRST_USBPOR 105
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#define SRST_VCODEC_A 112
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#define SRST_VCODEC_H 113
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#define SRST_VIO1_A 114
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#define SRST_HEVC 115
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#define SRST_VCODEC_NIU_A 116
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#define SRST_LCDC1_A 117
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#define SRST_LCDC1_H 118
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#define SRST_LCDC1_D 119
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#define SRST_GPU 120
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#define SRST_GPU_NIU_A 122
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#define SRST_DBG_P 131
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#endif
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