/* SPDX-License-Identifier: GPL-2.0+
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*
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* Copyright (C) 2020 Renesas Electronics Corp.
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*/
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#ifndef __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__
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#define __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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/* r8a7742 CPG Core Clocks */
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#define R8A7742_CLK_Z 0
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#define R8A7742_CLK_Z2 1
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#define R8A7742_CLK_ZG 2
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#define R8A7742_CLK_ZTR 3
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#define R8A7742_CLK_ZTRD2 4
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#define R8A7742_CLK_ZT 5
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#define R8A7742_CLK_ZX 6
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#define R8A7742_CLK_ZS 7
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#define R8A7742_CLK_HP 8
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#define R8A7742_CLK_B 9
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#define R8A7742_CLK_LB 10
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#define R8A7742_CLK_P 11
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#define R8A7742_CLK_CL 12
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#define R8A7742_CLK_M2 13
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#define R8A7742_CLK_ZB3 14
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#define R8A7742_CLK_ZB3D2 15
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#define R8A7742_CLK_DDR 16
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#define R8A7742_CLK_SDH 17
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#define R8A7742_CLK_SD0 18
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#define R8A7742_CLK_SD1 19
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#define R8A7742_CLK_SD2 20
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#define R8A7742_CLK_SD3 21
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#define R8A7742_CLK_MMC0 22
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#define R8A7742_CLK_MMC1 23
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#define R8A7742_CLK_MP 24
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#define R8A7742_CLK_QSPI 25
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#define R8A7742_CLK_CP 26
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#define R8A7742_CLK_RCAN 27
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#define R8A7742_CLK_R 28
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#define R8A7742_CLK_OSC 29
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#endif /* __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__ */
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