/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
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*/
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#ifndef __DT_BINDINGS_CLOCK_IMX27_H
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#define __DT_BINDINGS_CLOCK_IMX27_H
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#define IMX27_CLK_DUMMY 0
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#define IMX27_CLK_CKIH 1
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#define IMX27_CLK_CKIL 2
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#define IMX27_CLK_MPLL 3
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#define IMX27_CLK_SPLL 4
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#define IMX27_CLK_MPLL_MAIN2 5
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#define IMX27_CLK_AHB 6
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#define IMX27_CLK_IPG 7
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#define IMX27_CLK_NFC_DIV 8
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#define IMX27_CLK_PER1_DIV 9
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#define IMX27_CLK_PER2_DIV 10
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#define IMX27_CLK_PER3_DIV 11
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#define IMX27_CLK_PER4_DIV 12
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#define IMX27_CLK_VPU_SEL 13
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#define IMX27_CLK_VPU_DIV 14
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#define IMX27_CLK_USB_DIV 15
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#define IMX27_CLK_CPU_SEL 16
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#define IMX27_CLK_CLKO_SEL 17
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#define IMX27_CLK_CPU_DIV 18
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#define IMX27_CLK_CLKO_DIV 19
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#define IMX27_CLK_SSI1_SEL 20
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#define IMX27_CLK_SSI2_SEL 21
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#define IMX27_CLK_SSI1_DIV 22
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#define IMX27_CLK_SSI2_DIV 23
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#define IMX27_CLK_CLKO_EN 24
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#define IMX27_CLK_SSI2_IPG_GATE 25
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#define IMX27_CLK_SSI1_IPG_GATE 26
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#define IMX27_CLK_SLCDC_IPG_GATE 27
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#define IMX27_CLK_SDHC3_IPG_GATE 28
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#define IMX27_CLK_SDHC2_IPG_GATE 29
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#define IMX27_CLK_SDHC1_IPG_GATE 30
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#define IMX27_CLK_SCC_IPG_GATE 31
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#define IMX27_CLK_SAHARA_IPG_GATE 32
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#define IMX27_CLK_RTC_IPG_GATE 33
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#define IMX27_CLK_PWM_IPG_GATE 34
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#define IMX27_CLK_OWIRE_IPG_GATE 35
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#define IMX27_CLK_LCDC_IPG_GATE 36
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#define IMX27_CLK_KPP_IPG_GATE 37
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#define IMX27_CLK_IIM_IPG_GATE 38
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#define IMX27_CLK_I2C2_IPG_GATE 39
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#define IMX27_CLK_I2C1_IPG_GATE 40
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#define IMX27_CLK_GPT6_IPG_GATE 41
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#define IMX27_CLK_GPT5_IPG_GATE 42
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#define IMX27_CLK_GPT4_IPG_GATE 43
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#define IMX27_CLK_GPT3_IPG_GATE 44
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#define IMX27_CLK_GPT2_IPG_GATE 45
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#define IMX27_CLK_GPT1_IPG_GATE 46
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#define IMX27_CLK_GPIO_IPG_GATE 47
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#define IMX27_CLK_FEC_IPG_GATE 48
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#define IMX27_CLK_EMMA_IPG_GATE 49
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#define IMX27_CLK_DMA_IPG_GATE 50
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#define IMX27_CLK_CSPI3_IPG_GATE 51
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#define IMX27_CLK_CSPI2_IPG_GATE 52
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#define IMX27_CLK_CSPI1_IPG_GATE 53
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#define IMX27_CLK_NFC_BAUD_GATE 54
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#define IMX27_CLK_SSI2_BAUD_GATE 55
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#define IMX27_CLK_SSI1_BAUD_GATE 56
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#define IMX27_CLK_VPU_BAUD_GATE 57
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#define IMX27_CLK_PER4_GATE 58
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#define IMX27_CLK_PER3_GATE 59
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#define IMX27_CLK_PER2_GATE 60
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#define IMX27_CLK_PER1_GATE 61
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#define IMX27_CLK_USB_AHB_GATE 62
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#define IMX27_CLK_SLCDC_AHB_GATE 63
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#define IMX27_CLK_SAHARA_AHB_GATE 64
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#define IMX27_CLK_LCDC_AHB_GATE 65
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#define IMX27_CLK_VPU_AHB_GATE 66
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#define IMX27_CLK_FEC_AHB_GATE 67
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#define IMX27_CLK_EMMA_AHB_GATE 68
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#define IMX27_CLK_EMI_AHB_GATE 69
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#define IMX27_CLK_DMA_AHB_GATE 70
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#define IMX27_CLK_CSI_AHB_GATE 71
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#define IMX27_CLK_BROM_AHB_GATE 72
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#define IMX27_CLK_ATA_AHB_GATE 73
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#define IMX27_CLK_WDOG_IPG_GATE 74
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#define IMX27_CLK_USB_IPG_GATE 75
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#define IMX27_CLK_UART6_IPG_GATE 76
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#define IMX27_CLK_UART5_IPG_GATE 77
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#define IMX27_CLK_UART4_IPG_GATE 78
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#define IMX27_CLK_UART3_IPG_GATE 79
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#define IMX27_CLK_UART2_IPG_GATE 80
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#define IMX27_CLK_UART1_IPG_GATE 81
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#define IMX27_CLK_CKIH_DIV1P5 82
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#define IMX27_CLK_FPM 83
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#define IMX27_CLK_MPLL_OSC_SEL 84
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#define IMX27_CLK_MPLL_SEL 85
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#define IMX27_CLK_SPLL_GATE 86
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#define IMX27_CLK_MSHC_DIV 87
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#define IMX27_CLK_RTIC_IPG_GATE 88
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#define IMX27_CLK_MSHC_IPG_GATE 89
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#define IMX27_CLK_RTIC_AHB_GATE 90
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#define IMX27_CLK_MSHC_BAUD_GATE 91
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#define IMX27_CLK_CKIH_GATE 92
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#define IMX27_CLK_MAX 93
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#endif
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