/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Device Tree binding constants for HiSilicon Hi3670 SoC
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*
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* Copyright (c) 2001-2021, Huawei Tech. Co., Ltd.
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* Copyright (c) 2018 Linaro Ltd.
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*/
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#ifndef __DT_BINDINGS_CLOCK_HI3670_H
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#define __DT_BINDINGS_CLOCK_HI3670_H
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/* clk in stub clock */
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#define HI3670_CLK_STUB_CLUSTER0 0
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#define HI3670_CLK_STUB_CLUSTER1 1
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#define HI3670_CLK_STUB_GPU 2
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#define HI3670_CLK_STUB_DDR 3
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#define HI3670_CLK_STUB_DDR_VOTE 4
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#define HI3670_CLK_STUB_DDR_LIMIT 5
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#define HI3670_CLK_STUB_NUM 6
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/* clk in crg clock */
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#define HI3670_CLKIN_SYS 0
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#define HI3670_CLKIN_REF 1
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#define HI3670_CLK_FLL_SRC 2
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#define HI3670_CLK_PPLL0 3
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#define HI3670_CLK_PPLL1 4
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#define HI3670_CLK_PPLL2 5
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#define HI3670_CLK_PPLL3 6
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#define HI3670_CLK_PPLL4 7
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#define HI3670_CLK_PPLL6 8
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#define HI3670_CLK_PPLL7 9
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#define HI3670_CLK_PPLL_PCIE 10
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#define HI3670_CLK_PCIEPLL_REV 11
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#define HI3670_CLK_SCPLL 12
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#define HI3670_PCLK 13
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#define HI3670_CLK_UART0_DBG 14
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#define HI3670_CLK_UART6 15
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#define HI3670_OSC32K 16
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#define HI3670_OSC19M 17
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#define HI3670_CLK_480M 18
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#define HI3670_CLK_INVALID 19
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#define HI3670_CLK_DIV_SYSBUS 20
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#define HI3670_CLK_FACTOR_MMC 21
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#define HI3670_CLK_SD_SYS 22
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#define HI3670_CLK_SDIO_SYS 23
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#define HI3670_CLK_DIV_A53HPM 24
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#define HI3670_CLK_DIV_320M 25
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#define HI3670_PCLK_GATE_UART0 26
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#define HI3670_CLK_FACTOR_UART0 27
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#define HI3670_CLK_FACTOR_USB3PHY_PLL 28
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#define HI3670_CLK_GATE_ABB_USB 29
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#define HI3670_CLK_GATE_UFSPHY_REF 30
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#define HI3670_ICS_VOLT_HIGH 31
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#define HI3670_ICS_VOLT_MIDDLE 32
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#define HI3670_VENC_VOLT_HOLD 33
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#define HI3670_VDEC_VOLT_HOLD 34
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#define HI3670_EDC_VOLT_HOLD 35
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#define HI3670_CLK_ISP_SNCLK_FAC 36
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#define HI3670_CLK_FACTOR_RXDPHY 37
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#define HI3670_AUTODIV_SYSBUS 38
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#define HI3670_AUTODIV_EMMC0BUS 39
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#define HI3670_PCLK_ANDGT_MMC1_PCIE 40
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#define HI3670_CLK_GATE_VCODECBUS_GT 41
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#define HI3670_CLK_ANDGT_SD 42
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#define HI3670_CLK_SD_SYS_GT 43
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#define HI3670_CLK_ANDGT_SDIO 44
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#define HI3670_CLK_SDIO_SYS_GT 45
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#define HI3670_CLK_A53HPM_ANDGT 46
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#define HI3670_CLK_320M_PLL_GT 47
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#define HI3670_CLK_ANDGT_UARTH 48
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#define HI3670_CLK_ANDGT_UARTL 49
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#define HI3670_CLK_ANDGT_UART0 50
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#define HI3670_CLK_ANDGT_SPI 51
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#define HI3670_CLK_ANDGT_PCIEAXI 52
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#define HI3670_CLK_DIV_AO_ASP_GT 53
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#define HI3670_CLK_GATE_CSI_TRANS 54
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#define HI3670_CLK_GATE_DSI_TRANS 55
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#define HI3670_CLK_ANDGT_PTP 56
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#define HI3670_CLK_ANDGT_OUT0 57
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#define HI3670_CLK_ANDGT_OUT1 58
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#define HI3670_CLKGT_DP_AUDIO_PLL_AO 59
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#define HI3670_CLK_ANDGT_VDEC 60
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#define HI3670_CLK_ANDGT_VENC 61
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#define HI3670_CLK_ISP_SNCLK_ANGT 62
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#define HI3670_CLK_ANDGT_RXDPHY 63
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#define HI3670_CLK_ANDGT_ICS 64
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#define HI3670_AUTODIV_DMABUS 65
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#define HI3670_CLK_MUX_SYSBUS 66
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#define HI3670_CLK_MUX_VCODECBUS 67
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#define HI3670_CLK_MUX_SD_SYS 68
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#define HI3670_CLK_MUX_SD_PLL 69
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#define HI3670_CLK_MUX_SDIO_SYS 70
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#define HI3670_CLK_MUX_SDIO_PLL 71
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#define HI3670_CLK_MUX_A53HPM 72
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#define HI3670_CLK_MUX_320M 73
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#define HI3670_CLK_MUX_UARTH 74
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#define HI3670_CLK_MUX_UARTL 75
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#define HI3670_CLK_MUX_UART0 76
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#define HI3670_CLK_MUX_I2C 77
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#define HI3670_CLK_MUX_SPI 78
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#define HI3670_CLK_MUX_PCIEAXI 79
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#define HI3670_CLK_MUX_AO_ASP 80
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#define HI3670_CLK_MUX_VDEC 81
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#define HI3670_CLK_MUX_VENC 82
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#define HI3670_CLK_ISP_SNCLK_MUX0 83
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#define HI3670_CLK_ISP_SNCLK_MUX1 84
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#define HI3670_CLK_ISP_SNCLK_MUX2 85
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#define HI3670_CLK_MUX_RXDPHY_CFG 86
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#define HI3670_CLK_MUX_ICS 87
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#define HI3670_CLK_DIV_CFGBUS 88
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#define HI3670_CLK_DIV_MMC0BUS 89
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#define HI3670_CLK_DIV_MMC1BUS 90
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#define HI3670_PCLK_DIV_MMC1_PCIE 91
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#define HI3670_CLK_DIV_VCODECBUS 92
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#define HI3670_CLK_DIV_SD 93
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#define HI3670_CLK_DIV_SDIO 94
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#define HI3670_CLK_DIV_UARTH 95
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#define HI3670_CLK_DIV_UARTL 96
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#define HI3670_CLK_DIV_UART0 97
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#define HI3670_CLK_DIV_I2C 98
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#define HI3670_CLK_DIV_SPI 99
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#define HI3670_CLK_DIV_PCIEAXI 100
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#define HI3670_CLK_DIV_AO_ASP 101
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#define HI3670_CLK_DIV_CSI_TRANS 102
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#define HI3670_CLK_DIV_DSI_TRANS 103
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#define HI3670_CLK_DIV_PTP 104
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#define HI3670_CLK_DIV_CLKOUT0_PLL 105
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#define HI3670_CLK_DIV_CLKOUT1_PLL 106
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#define HI3670_CLKDIV_DP_AUDIO_PLL_AO 107
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#define HI3670_CLK_DIV_VDEC 108
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#define HI3670_CLK_DIV_VENC 109
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#define HI3670_CLK_ISP_SNCLK_DIV0 110
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#define HI3670_CLK_ISP_SNCLK_DIV1 111
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#define HI3670_CLK_ISP_SNCLK_DIV2 112
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#define HI3670_CLK_DIV_ICS 113
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#define HI3670_PPLL1_EN_ACPU 114
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#define HI3670_PPLL2_EN_ACPU 115
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#define HI3670_PPLL3_EN_ACPU 116
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#define HI3670_PPLL1_GT_CPU 117
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#define HI3670_PPLL2_GT_CPU 118
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#define HI3670_PPLL3_GT_CPU 119
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#define HI3670_CLK_GATE_PPLL2_MEDIA 120
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#define HI3670_CLK_GATE_PPLL3_MEDIA 121
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#define HI3670_CLK_GATE_PPLL4_MEDIA 122
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#define HI3670_CLK_GATE_PPLL6_MEDIA 123
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#define HI3670_CLK_GATE_PPLL7_MEDIA 124
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#define HI3670_PCLK_GPIO0 125
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#define HI3670_PCLK_GPIO1 126
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#define HI3670_PCLK_GPIO2 127
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#define HI3670_PCLK_GPIO3 128
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#define HI3670_PCLK_GPIO4 129
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#define HI3670_PCLK_GPIO5 130
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#define HI3670_PCLK_GPIO6 131
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#define HI3670_PCLK_GPIO7 132
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#define HI3670_PCLK_GPIO8 133
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#define HI3670_PCLK_GPIO9 134
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#define HI3670_PCLK_GPIO10 135
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#define HI3670_PCLK_GPIO11 136
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#define HI3670_PCLK_GPIO12 137
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#define HI3670_PCLK_GPIO13 138
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#define HI3670_PCLK_GPIO14 139
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#define HI3670_PCLK_GPIO15 140
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#define HI3670_PCLK_GPIO16 141
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#define HI3670_PCLK_GPIO17 142
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#define HI3670_PCLK_GPIO20 143
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#define HI3670_PCLK_GPIO21 144
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#define HI3670_PCLK_GATE_DSI0 145
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#define HI3670_PCLK_GATE_DSI1 146
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#define HI3670_HCLK_GATE_USB3OTG 147
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#define HI3670_ACLK_GATE_USB3DVFS 148
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#define HI3670_HCLK_GATE_SDIO 149
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#define HI3670_PCLK_GATE_PCIE_SYS 150
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#define HI3670_PCLK_GATE_PCIE_PHY 151
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#define HI3670_PCLK_GATE_MMC1_PCIE 152
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#define HI3670_PCLK_GATE_MMC0_IOC 153
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#define HI3670_PCLK_GATE_MMC1_IOC 154
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#define HI3670_CLK_GATE_DMAC 155
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#define HI3670_CLK_GATE_VCODECBUS2DDR 156
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#define HI3670_CLK_CCI400_BYPASS 157
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#define HI3670_CLK_GATE_CCI400 158
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#define HI3670_CLK_GATE_SD 159
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#define HI3670_HCLK_GATE_SD 160
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#define HI3670_CLK_GATE_SDIO 161
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#define HI3670_CLK_GATE_A57HPM 162
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#define HI3670_CLK_GATE_A53HPM 163
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#define HI3670_CLK_GATE_PA_A53 164
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#define HI3670_CLK_GATE_PA_A57 165
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#define HI3670_CLK_GATE_PA_G3D 166
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#define HI3670_CLK_GATE_GPUHPM 167
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#define HI3670_CLK_GATE_PERIHPM 168
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#define HI3670_CLK_GATE_AOHPM 169
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#define HI3670_CLK_GATE_UART1 170
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#define HI3670_CLK_GATE_UART4 171
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#define HI3670_PCLK_GATE_UART1 172
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#define HI3670_PCLK_GATE_UART4 173
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#define HI3670_CLK_GATE_UART2 174
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#define HI3670_CLK_GATE_UART5 175
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#define HI3670_PCLK_GATE_UART2 176
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#define HI3670_PCLK_GATE_UART5 177
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#define HI3670_CLK_GATE_UART0 178
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#define HI3670_CLK_GATE_I2C3 179
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#define HI3670_CLK_GATE_I2C4 180
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#define HI3670_CLK_GATE_I2C7 181
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#define HI3670_PCLK_GATE_I2C3 182
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#define HI3670_PCLK_GATE_I2C4 183
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#define HI3670_PCLK_GATE_I2C7 184
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#define HI3670_CLK_GATE_SPI1 185
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#define HI3670_CLK_GATE_SPI4 186
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#define HI3670_PCLK_GATE_SPI1 187
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#define HI3670_PCLK_GATE_SPI4 188
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#define HI3670_CLK_GATE_USB3OTG_REF 189
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#define HI3670_CLK_GATE_USB2PHY_REF 190
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#define HI3670_CLK_GATE_PCIEAUX 191
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#define HI3670_ACLK_GATE_PCIE 192
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#define HI3670_CLK_GATE_MMC1_PCIEAXI 193
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#define HI3670_CLK_GATE_PCIEPHY_REF 194
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#define HI3670_CLK_GATE_PCIE_DEBOUNCE 195
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#define HI3670_CLK_GATE_PCIEIO 196
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#define HI3670_CLK_GATE_PCIE_HP 197
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#define HI3670_CLK_GATE_AO_ASP 198
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#define HI3670_PCLK_GATE_PCTRL 199
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#define HI3670_CLK_CSI_TRANS_GT 200
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#define HI3670_CLK_DSI_TRANS_GT 201
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#define HI3670_CLK_GATE_PWM 202
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#define HI3670_ABB_AUDIO_EN0 203
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#define HI3670_ABB_AUDIO_EN1 204
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#define HI3670_ABB_AUDIO_GT_EN0 205
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#define HI3670_ABB_AUDIO_GT_EN1 206
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#define HI3670_CLK_GATE_DP_AUDIO_PLL_AO 207
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#define HI3670_PERI_VOLT_HOLD 208
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#define HI3670_PERI_VOLT_MIDDLE 209
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#define HI3670_CLK_GATE_ISP_SNCLK0 210
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#define HI3670_CLK_GATE_ISP_SNCLK1 211
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#define HI3670_CLK_GATE_ISP_SNCLK2 212
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#define HI3670_CLK_GATE_RXDPHY0_CFG 213
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#define HI3670_CLK_GATE_RXDPHY1_CFG 214
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#define HI3670_CLK_GATE_RXDPHY2_CFG 215
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#define HI3670_CLK_GATE_TXDPHY0_CFG 216
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#define HI3670_CLK_GATE_TXDPHY0_REF 217
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#define HI3670_CLK_GATE_TXDPHY1_CFG 218
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#define HI3670_CLK_GATE_TXDPHY1_REF 219
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#define HI3670_CLK_GATE_MEDIA_TCXO 220
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/* clk in sctrl */
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#define HI3670_CLK_ANDGT_IOPERI 0
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#define HI3670_CLKANDGT_ASP_SUBSYS_PERI 1
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#define HI3670_CLK_ANGT_ASP_SUBSYS 2
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#define HI3670_CLK_MUX_UFS_SUBSYS 3
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#define HI3670_CLK_MUX_CLKOUT0 4
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#define HI3670_CLK_MUX_CLKOUT1 5
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#define HI3670_CLK_MUX_ASP_SUBSYS_PERI 6
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#define HI3670_CLK_MUX_ASP_PLL 7
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#define HI3670_CLK_DIV_AOBUS 8
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#define HI3670_CLK_DIV_UFS_SUBSYS 9
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#define HI3670_CLK_DIV_IOPERI 10
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#define HI3670_CLK_DIV_CLKOUT0_TCXO 11
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#define HI3670_CLK_DIV_CLKOUT1_TCXO 12
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#define HI3670_CLK_ASP_SUBSYS_PERI_DIV 13
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#define HI3670_CLK_DIV_ASP_SUBSYS 14
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#define HI3670_PPLL0_EN_ACPU 15
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#define HI3670_PPLL0_GT_CPU 16
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#define HI3670_CLK_GATE_PPLL0_MEDIA 17
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#define HI3670_PCLK_GPIO18 18
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#define HI3670_PCLK_GPIO19 19
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#define HI3670_CLK_GATE_SPI 20
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#define HI3670_PCLK_GATE_SPI 21
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#define HI3670_CLK_GATE_UFS_SUBSYS 22
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#define HI3670_CLK_GATE_UFSIO_REF 23
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#define HI3670_PCLK_AO_GPIO0 24
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#define HI3670_PCLK_AO_GPIO1 25
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#define HI3670_PCLK_AO_GPIO2 26
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#define HI3670_PCLK_AO_GPIO3 27
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#define HI3670_PCLK_AO_GPIO4 28
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#define HI3670_PCLK_AO_GPIO5 29
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#define HI3670_PCLK_AO_GPIO6 30
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#define HI3670_CLK_GATE_OUT0 31
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#define HI3670_CLK_GATE_OUT1 32
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#define HI3670_PCLK_GATE_SYSCNT 33
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#define HI3670_CLK_GATE_SYSCNT 34
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#define HI3670_CLK_GATE_ASP_SUBSYS_PERI 35
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#define HI3670_CLK_GATE_ASP_SUBSYS 36
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#define HI3670_CLK_GATE_ASP_TCXO 37
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#define HI3670_CLK_GATE_DP_AUDIO_PLL 38
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/* clk in pmuctrl */
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#define HI3670_GATE_ABB_192 0
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/* clk in pctrl */
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#define HI3670_GATE_UFS_TCXO_EN 0
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#define HI3670_GATE_USB_TCXO_EN 1
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/* clk in iomcu */
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#define HI3670_CLK_GATE_I2C0 0
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#define HI3670_CLK_GATE_I2C1 1
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#define HI3670_CLK_GATE_I2C2 2
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#define HI3670_CLK_GATE_SPI0 3
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#define HI3670_CLK_GATE_SPI2 4
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#define HI3670_CLK_GATE_UART3 5
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#define HI3670_CLK_I2C0_GATE_IOMCU 6
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#define HI3670_CLK_I2C1_GATE_IOMCU 7
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#define HI3670_CLK_I2C2_GATE_IOMCU 8
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#define HI3670_CLK_SPI0_GATE_IOMCU 9
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#define HI3670_CLK_SPI2_GATE_IOMCU 10
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#define HI3670_CLK_UART3_GATE_IOMCU 11
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#define HI3670_CLK_GATE_PERI0_IOMCU 12
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/* clk in media1 */
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#define HI3670_CLK_GATE_VIVOBUS_ANDGT 0
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#define HI3670_CLK_ANDGT_EDC0 1
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#define HI3670_CLK_ANDGT_LDI0 2
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#define HI3670_CLK_ANDGT_LDI1 3
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#define HI3670_CLK_MMBUF_PLL_ANDGT 4
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#define HI3670_PCLK_MMBUF_ANDGT 5
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#define HI3670_CLK_MUX_VIVOBUS 6
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#define HI3670_CLK_MUX_EDC0 7
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#define HI3670_CLK_MUX_LDI0 8
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#define HI3670_CLK_MUX_LDI1 9
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#define HI3670_CLK_SW_MMBUF 10
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#define HI3670_CLK_DIV_VIVOBUS 11
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#define HI3670_CLK_DIV_EDC0 12
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#define HI3670_CLK_DIV_LDI0 13
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#define HI3670_CLK_DIV_LDI1 14
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#define HI3670_ACLK_DIV_MMBUF 15
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#define HI3670_PCLK_DIV_MMBUF 16
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#define HI3670_ACLK_GATE_NOC_DSS 17
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#define HI3670_PCLK_GATE_NOC_DSS_CFG 18
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#define HI3670_PCLK_GATE_MMBUF_CFG 19
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#define HI3670_PCLK_GATE_DISP_NOC_SUBSYS 20
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#define HI3670_ACLK_GATE_DISP_NOC_SUBSYS 21
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#define HI3670_PCLK_GATE_DSS 22
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#define HI3670_ACLK_GATE_DSS 23
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#define HI3670_CLK_GATE_VIVOBUSFREQ 24
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#define HI3670_CLK_GATE_EDC0 25
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#define HI3670_CLK_GATE_LDI0 26
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#define HI3670_CLK_GATE_LDI1FREQ 27
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#define HI3670_CLK_GATE_BRG 28
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#define HI3670_ACLK_GATE_ASC 29
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#define HI3670_CLK_GATE_DSS_AXI_MM 30
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#define HI3670_CLK_GATE_MMBUF 31
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#define HI3670_PCLK_GATE_MMBUF 32
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#define HI3670_CLK_GATE_ATDIV_VIVO 33
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/* clk in media2 */
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#define HI3670_CLK_GATE_VDECFREQ 0
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#define HI3670_CLK_GATE_VENCFREQ 1
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#define HI3670_CLK_GATE_ICSFREQ 2
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#endif /* __DT_BINDINGS_CLOCK_HI3670_H */
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