/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __DT_BINDINGS_CLOCK_EFM32_CMU_H
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#define __DT_BINDINGS_CLOCK_EFM32_CMU_H
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#define clk_HFXO 0
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#define clk_HFRCO 1
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#define clk_LFXO 2
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#define clk_LFRCO 3
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#define clk_ULFRCO 4
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#define clk_AUXHFRCO 5
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#define clk_HFCLKNODIV 6
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#define clk_HFCLK 7
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#define clk_HFPERCLK 8
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#define clk_HFCORECLK 9
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#define clk_LFACLK 10
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#define clk_LFBCLK 11
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#define clk_WDOGCLK 12
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#define clk_HFCORECLKDMA 13
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#define clk_HFCORECLKAES 14
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#define clk_HFCORECLKUSBC 15
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#define clk_HFCORECLKUSB 16
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#define clk_HFCORECLKLE 17
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#define clk_HFCORECLKEBI 18
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#define clk_HFPERCLKUSART0 19
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#define clk_HFPERCLKUSART1 20
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#define clk_HFPERCLKUSART2 21
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#define clk_HFPERCLKUART0 22
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#define clk_HFPERCLKUART1 23
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#define clk_HFPERCLKTIMER0 24
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#define clk_HFPERCLKTIMER1 25
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#define clk_HFPERCLKTIMER2 26
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#define clk_HFPERCLKTIMER3 27
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#define clk_HFPERCLKACMP0 28
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#define clk_HFPERCLKACMP1 29
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#define clk_HFPERCLKI2C0 30
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#define clk_HFPERCLKI2C1 31
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#define clk_HFPERCLKGPIO 32
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#define clk_HFPERCLKVCMP 33
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#define clk_HFPERCLKPRS 34
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#define clk_HFPERCLKADC0 35
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#define clk_HFPERCLKDAC0 36
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#endif /* __DT_BINDINGS_CLOCK_EFM32_CMU_H */
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