/* SPDX-License-Identifier: GPL-2.0 */
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/* -*- mode: c; c-basic-offset: 8 -*- */
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/* Driver for 53c700 and 53c700-66 chips from NCR and Symbios
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*
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* Copyright (C) 2001 by James.Bottomley@HansenPartnership.com
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*/
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#ifndef _53C700_H
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#define _53C700_H
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#include <linux/interrupt.h>
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#include <asm/io.h>
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#include <scsi/scsi_device.h>
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#include <scsi/scsi_cmnd.h>
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/* Turn on for general debugging---too verbose for normal use */
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#undef NCR_700_DEBUG
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/* Debug the tag queues, checking hash queue allocation and deallocation
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* and search for duplicate tags */
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#undef NCR_700_TAG_DEBUG
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#ifdef NCR_700_DEBUG
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#define DEBUG(x) printk x
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#define DDEBUG(prefix, sdev, fmt, a...) \
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sdev_printk(prefix, sdev, fmt, ##a)
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#define CDEBUG(prefix, scmd, fmt, a...) \
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scmd_printk(prefix, scmd, fmt, ##a)
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#else
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#define DEBUG(x) do {} while (0)
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#define DDEBUG(prefix, scmd, fmt, a...) do {} while (0)
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#define CDEBUG(prefix, scmd, fmt, a...) do {} while (0)
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#endif
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/* The number of available command slots */
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#define NCR_700_COMMAND_SLOTS_PER_HOST 64
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/* The maximum number of Scatter Gathers we allow */
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#define NCR_700_SG_SEGMENTS 32
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/* The maximum number of luns (make this of the form 2^n) */
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#define NCR_700_MAX_LUNS 32
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#define NCR_700_LUN_MASK (NCR_700_MAX_LUNS - 1)
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/* Maximum number of tags the driver ever allows per device */
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#define NCR_700_MAX_TAGS 16
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/* Tag depth the driver starts out with (can be altered in sysfs) */
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#define NCR_700_DEFAULT_TAGS 4
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/* This is the default number of commands per LUN in the untagged case.
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* two is a good value because it means we can have one command active and
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* one command fully prepared and waiting
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*/
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#define NCR_700_CMD_PER_LUN 2
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/* magic byte identifying an internally generated REQUEST_SENSE command */
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#define NCR_700_INTERNAL_SENSE_MAGIC 0x42
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struct NCR_700_Host_Parameters;
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/* These are the externally used routines */
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struct Scsi_Host *NCR_700_detect(struct scsi_host_template *,
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struct NCR_700_Host_Parameters *, struct device *);
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int NCR_700_release(struct Scsi_Host *host);
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irqreturn_t NCR_700_intr(int, void *);
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enum NCR_700_Host_State {
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NCR_700_HOST_BUSY,
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NCR_700_HOST_FREE,
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};
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struct NCR_700_SG_List {
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/* The following is a script fragment to move the buffer onto the
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* bus and then link the next fragment or return */
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#define SCRIPT_MOVE_DATA_IN 0x09000000
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#define SCRIPT_MOVE_DATA_OUT 0x08000000
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__u32 ins;
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__u32 pAddr;
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#define SCRIPT_NOP 0x80000000
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#define SCRIPT_RETURN 0x90080000
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};
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struct NCR_700_Device_Parameters {
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/* space for creating a request sense command. Really, except
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* for the annoying SCSI-2 requirement for LUN information in
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* cmnd[1], this could be in static storage */
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unsigned char cmnd[MAX_COMMAND_SIZE];
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__u8 depth;
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struct scsi_cmnd *current_cmnd; /* currently active command */
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};
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/* The SYNC negotiation sequence looks like:
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*
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* If DEV_NEGOTIATED_SYNC not set, tack and SDTR message on to the
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* initial identify for the device and set DEV_BEGIN_SYNC_NEGOTIATION
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* If we get an SDTR reply, work out the SXFER parameters, squirrel
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* them away here, clear DEV_BEGIN_SYNC_NEGOTIATION and set
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* DEV_NEGOTIATED_SYNC. If we get a REJECT msg, squirrel
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*
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*
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* 0:7 SXFER_REG negotiated value for this device
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* 8:15 Current queue depth
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* 16 negotiated SYNC flag
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* 17 begin SYNC negotiation flag
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* 18 device supports tag queueing */
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#define NCR_700_DEV_NEGOTIATED_SYNC (1<<16)
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#define NCR_700_DEV_BEGIN_SYNC_NEGOTIATION (1<<17)
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#define NCR_700_DEV_PRINT_SYNC_NEGOTIATION (1<<19)
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static inline char *NCR_700_get_sense_cmnd(struct scsi_device *SDp)
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{
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struct NCR_700_Device_Parameters *hostdata = SDp->hostdata;
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return hostdata->cmnd;
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}
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static inline void
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NCR_700_set_depth(struct scsi_device *SDp, __u8 depth)
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{
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struct NCR_700_Device_Parameters *hostdata = SDp->hostdata;
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hostdata->depth = depth;
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}
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static inline __u8
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NCR_700_get_depth(struct scsi_device *SDp)
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{
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struct NCR_700_Device_Parameters *hostdata = SDp->hostdata;
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return hostdata->depth;
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}
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static inline int
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NCR_700_is_flag_set(struct scsi_device *SDp, __u32 flag)
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{
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return (spi_flags(SDp->sdev_target) & flag) == flag;
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}
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static inline int
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NCR_700_is_flag_clear(struct scsi_device *SDp, __u32 flag)
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{
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return (spi_flags(SDp->sdev_target) & flag) == 0;
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}
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static inline void
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NCR_700_set_flag(struct scsi_device *SDp, __u32 flag)
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{
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spi_flags(SDp->sdev_target) |= flag;
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}
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static inline void
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NCR_700_clear_flag(struct scsi_device *SDp, __u32 flag)
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{
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spi_flags(SDp->sdev_target) &= ~flag;
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}
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enum NCR_700_tag_neg_state {
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NCR_700_START_TAG_NEGOTIATION = 0,
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NCR_700_DURING_TAG_NEGOTIATION = 1,
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NCR_700_FINISHED_TAG_NEGOTIATION = 2,
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};
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static inline enum NCR_700_tag_neg_state
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NCR_700_get_tag_neg_state(struct scsi_device *SDp)
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{
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return (enum NCR_700_tag_neg_state)((spi_flags(SDp->sdev_target)>>20) & 0x3);
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}
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static inline void
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NCR_700_set_tag_neg_state(struct scsi_device *SDp,
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enum NCR_700_tag_neg_state state)
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{
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/* clear the slot */
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spi_flags(SDp->sdev_target) &= ~(0x3 << 20);
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spi_flags(SDp->sdev_target) |= ((__u32)state) << 20;
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}
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struct NCR_700_command_slot {
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struct NCR_700_SG_List SG[NCR_700_SG_SEGMENTS+1];
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struct NCR_700_SG_List *pSG;
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#define NCR_700_SLOT_MASK 0xFC
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#define NCR_700_SLOT_MAGIC 0xb8
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#define NCR_700_SLOT_FREE (0|NCR_700_SLOT_MAGIC) /* slot may be used */
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#define NCR_700_SLOT_BUSY (1|NCR_700_SLOT_MAGIC) /* slot has command active on HA */
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#define NCR_700_SLOT_QUEUED (2|NCR_700_SLOT_MAGIC) /* slot has command to be made active on HA */
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__u8 state;
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#define NCR_700_FLAG_AUTOSENSE 0x01
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__u8 flags;
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__u8 pad1[2]; /* Needed for m68k where min alignment is 2 bytes */
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int tag;
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__u32 resume_offset;
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struct scsi_cmnd *cmnd;
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/* The pci_mapped address of the actual command in cmnd */
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dma_addr_t pCmd;
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__u32 temp;
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/* if this command is a pci_single mapping, holds the dma address
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* for later unmapping in the done routine */
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dma_addr_t dma_handle;
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/* historical remnant, now used to link free commands */
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struct NCR_700_command_slot *ITL_forw;
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};
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struct NCR_700_Host_Parameters {
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/* These must be filled in by the calling driver */
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int clock; /* board clock speed in MHz */
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void __iomem *base; /* the base for the port (copied to host) */
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struct device *dev;
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__u32 dmode_extra; /* adjustable bus settings */
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__u32 dcntl_extra; /* adjustable bus settings */
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__u32 ctest7_extra; /* adjustable bus settings */
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__u32 differential:1; /* if we are differential */
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#ifdef CONFIG_53C700_LE_ON_BE
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/* This option is for HP only. Set it if your chip is wired for
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* little endian on this platform (which is big endian) */
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__u32 force_le_on_be:1;
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#endif
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__u32 chip710:1; /* set if really a 710 not 700 */
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__u32 burst_length:4; /* set to 0 to disable 710 bursting */
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__u32 noncoherent:1; /* needs to use non-coherent DMA */
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/* NOTHING BELOW HERE NEEDS ALTERING */
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__u32 fast:1; /* if we can alter the SCSI bus clock
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speed (so can negiotiate sync) */
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int sync_clock; /* The speed of the SYNC core */
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__u32 *script; /* pointer to script location */
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__u32 pScript; /* physical mem addr of script */
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enum NCR_700_Host_State state; /* protected by state lock */
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struct scsi_cmnd *cmd;
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/* Note: pScript contains the single consistent block of
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* memory. All the msgin, msgout and status are allocated in
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* this memory too (at separate cache lines). TOTAL_MEM_SIZE
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* represents the total size of this area */
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#define MSG_ARRAY_SIZE 8
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#define MSGOUT_OFFSET (L1_CACHE_ALIGN(sizeof(SCRIPT)))
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__u8 *msgout;
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#define MSGIN_OFFSET (MSGOUT_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE))
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__u8 *msgin;
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#define STATUS_OFFSET (MSGIN_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE))
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__u8 *status;
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#define SLOTS_OFFSET (STATUS_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE))
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struct NCR_700_command_slot *slots;
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#define TOTAL_MEM_SIZE (SLOTS_OFFSET + L1_CACHE_ALIGN(sizeof(struct NCR_700_command_slot) * NCR_700_COMMAND_SLOTS_PER_HOST))
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int saved_slot_position;
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int command_slot_count; /* protected by state lock */
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__u8 tag_negotiated;
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__u8 rev;
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__u8 reselection_id;
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__u8 min_period;
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/* Free list, singly linked by ITL_forw elements */
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struct NCR_700_command_slot *free_list;
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/* Completion for waited for ops, like reset, abort or
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* device reset.
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*
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* NOTE: relies on single threading in the error handler to
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* have only one outstanding at once */
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struct completion *eh_complete;
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};
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/*
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* 53C700 Register Interface - the offset from the Selected base
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* I/O address */
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#ifdef CONFIG_53C700_LE_ON_BE
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#define bE (hostdata->force_le_on_be ? 0 : 3)
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#define bSWAP (hostdata->force_le_on_be)
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#define bEBus (!hostdata->force_le_on_be)
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#elif defined(__BIG_ENDIAN)
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#define bE 3
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#define bSWAP 0
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#elif defined(__LITTLE_ENDIAN)
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#define bE 0
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#define bSWAP 0
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#else
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#error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined, did you include byteorder.h?"
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#endif
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#ifndef bEBus
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#ifdef CONFIG_53C700_BE_BUS
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#define bEBus 1
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#else
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#define bEBus 0
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#endif
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#endif
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#define bS_to_cpu(x) (bSWAP ? le32_to_cpu(x) : (x))
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#define bS_to_host(x) (bSWAP ? cpu_to_le32(x) : (x))
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/* NOTE: These registers are in the LE register space only, the required byte
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* swapping is done by the NCR_700_{read|write}[b] functions */
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#define SCNTL0_REG 0x00
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#define FULL_ARBITRATION 0xc0
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#define PARITY 0x08
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#define ENABLE_PARITY 0x04
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#define AUTO_ATN 0x02
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#define SCNTL1_REG 0x01
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#define SLOW_BUS 0x80
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#define ENABLE_SELECT 0x20
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#define ASSERT_RST 0x08
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#define ASSERT_EVEN_PARITY 0x04
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#define SDID_REG 0x02
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#define SIEN_REG 0x03
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#define PHASE_MM_INT 0x80
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#define FUNC_COMP_INT 0x40
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#define SEL_TIMEOUT_INT 0x20
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#define SELECT_INT 0x10
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#define GROSS_ERR_INT 0x08
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#define UX_DISC_INT 0x04
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#define RST_INT 0x02
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#define PAR_ERR_INT 0x01
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#define SCID_REG 0x04
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#define SXFER_REG 0x05
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#define ASYNC_OPERATION 0x00
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#define SODL_REG 0x06
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#define SOCL_REG 0x07
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#define SFBR_REG 0x08
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#define SIDL_REG 0x09
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#define SBDL_REG 0x0A
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#define SBCL_REG 0x0B
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/* read bits */
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#define SBCL_IO 0x01
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/*write bits */
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#define SYNC_DIV_AS_ASYNC 0x00
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#define SYNC_DIV_1_0 0x01
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#define SYNC_DIV_1_5 0x02
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#define SYNC_DIV_2_0 0x03
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#define DSTAT_REG 0x0C
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#define ILGL_INST_DETECTED 0x01
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#define WATCH_DOG_INTERRUPT 0x02
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#define SCRIPT_INT_RECEIVED 0x04
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#define ABORTED 0x10
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#define SSTAT0_REG 0x0D
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#define PARITY_ERROR 0x01
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#define SCSI_RESET_DETECTED 0x02
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#define UNEXPECTED_DISCONNECT 0x04
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#define SCSI_GROSS_ERROR 0x08
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#define SELECTED 0x10
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#define SELECTION_TIMEOUT 0x20
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#define FUNCTION_COMPLETE 0x40
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#define PHASE_MISMATCH 0x80
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#define SSTAT1_REG 0x0E
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#define SIDL_REG_FULL 0x80
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#define SODR_REG_FULL 0x40
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#define SODL_REG_FULL 0x20
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#define SSTAT2_REG 0x0F
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#define CTEST0_REG 0x14
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#define BTB_TIMER_DISABLE 0x40
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#define CTEST1_REG 0x15
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#define CTEST2_REG 0x16
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#define CTEST3_REG 0x17
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#define CTEST4_REG 0x18
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#define DISABLE_FIFO 0x00
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#define SLBE 0x10
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#define SFWR 0x08
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#define BYTE_LANE0 0x04
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#define BYTE_LANE1 0x05
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#define BYTE_LANE2 0x06
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#define BYTE_LANE3 0x07
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#define SCSI_ZMODE 0x20
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#define ZMODE 0x40
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#define CTEST5_REG 0x19
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#define MASTER_CONTROL 0x10
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#define DMA_DIRECTION 0x08
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#define CTEST7_REG 0x1B
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#define BURST_DISABLE 0x80 /* 710 only */
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#define SEL_TIMEOUT_DISABLE 0x10 /* 710 only */
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#define DFP 0x08
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#define EVP 0x04
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#define CTEST7_TT1 0x02
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#define DIFF 0x01
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#define CTEST6_REG 0x1A
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#define TEMP_REG 0x1C
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#define DFIFO_REG 0x20
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#define FLUSH_DMA_FIFO 0x80
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#define CLR_FIFO 0x40
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#define ISTAT_REG 0x21
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#define ABORT_OPERATION 0x80
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#define SOFTWARE_RESET_710 0x40
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#define DMA_INT_PENDING 0x01
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#define SCSI_INT_PENDING 0x02
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#define CONNECTED 0x08
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#define CTEST8_REG 0x22
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#define LAST_DIS_ENBL 0x01
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#define SHORTEN_FILTERING 0x04
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#define ENABLE_ACTIVE_NEGATION 0x10
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#define GENERATE_RECEIVE_PARITY 0x20
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#define CLR_FIFO_710 0x04
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#define FLUSH_DMA_FIFO_710 0x08
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#define CTEST9_REG 0x23
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#define DBC_REG 0x24
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#define DCMD_REG 0x27
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#define DNAD_REG 0x28
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#define DIEN_REG 0x39
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#define BUS_FAULT 0x20
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#define ABORT_INT 0x10
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#define INT_INST_INT 0x04
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#define WD_INT 0x02
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#define ILGL_INST_INT 0x01
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#define DCNTL_REG 0x3B
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#define SOFTWARE_RESET 0x01
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#define COMPAT_700_MODE 0x01
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#define SCRPTS_16BITS 0x20
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#define EA_710 0x20
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#define ASYNC_DIV_2_0 0x00
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#define ASYNC_DIV_1_5 0x40
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#define ASYNC_DIV_1_0 0x80
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#define ASYNC_DIV_3_0 0xc0
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#define DMODE_710_REG 0x38
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#define DMODE_700_REG 0x34
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#define BURST_LENGTH_1 0x00
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#define BURST_LENGTH_2 0x40
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#define BURST_LENGTH_4 0x80
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#define BURST_LENGTH_8 0xC0
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#define DMODE_FC1 0x10
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#define DMODE_FC2 0x20
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#define BW16 32
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#define MODE_286 16
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#define IO_XFER 8
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#define FIXED_ADDR 4
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#define DSP_REG 0x2C
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#define DSPS_REG 0x30
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/* Parameters to begin SDTR negotiations. Empirically, I find that
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* the 53c700-66 cannot handle an offset >8, so don't change this */
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#define NCR_700_MAX_OFFSET 8
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/* Was hoping the max offset would be greater for the 710, but
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* empirically it seems to be 8 also */
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#define NCR_710_MAX_OFFSET 8
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#define NCR_700_MIN_XFERP 1
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#define NCR_710_MIN_XFERP 0
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#define NCR_700_MIN_PERIOD 25 /* for SDTR message, 100ns */
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#define script_patch_32(h, script, symbol, value) \
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{ \
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int i; \
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dma_addr_t da = value; \
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for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \
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__u32 val = bS_to_cpu((script)[A_##symbol##_used[i]]) + da; \
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(script)[A_##symbol##_used[i]] = bS_to_host(val); \
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dma_sync_to_dev((h), &(script)[A_##symbol##_used[i]], 4); \
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DEBUG((" script, patching %s at %d to %pad\n", \
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#symbol, A_##symbol##_used[i], &da)); \
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} \
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}
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#define script_patch_32_abs(h, script, symbol, value) \
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{ \
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int i; \
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dma_addr_t da = value; \
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for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \
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(script)[A_##symbol##_used[i]] = bS_to_host(da); \
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dma_sync_to_dev((h), &(script)[A_##symbol##_used[i]], 4); \
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DEBUG((" script, patching %s at %d to %pad\n", \
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#symbol, A_##symbol##_used[i], &da)); \
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} \
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}
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/* Used for patching the SCSI ID in the SELECT instruction */
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#define script_patch_ID(h, script, symbol, value) \
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{ \
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int i; \
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for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \
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__u32 val = bS_to_cpu((script)[A_##symbol##_used[i]]); \
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val &= 0xff00ffff; \
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val |= ((value) & 0xff) << 16; \
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(script)[A_##symbol##_used[i]] = bS_to_host(val); \
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dma_sync_to_dev((h), &(script)[A_##symbol##_used[i]], 4); \
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DEBUG((" script, patching ID field %s at %d to 0x%x\n", \
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#symbol, A_##symbol##_used[i], val)); \
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} \
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}
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#define script_patch_16(h, script, symbol, value) \
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{ \
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int i; \
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for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \
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__u32 val = bS_to_cpu((script)[A_##symbol##_used[i]]); \
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val &= 0xffff0000; \
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val |= ((value) & 0xffff); \
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(script)[A_##symbol##_used[i]] = bS_to_host(val); \
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dma_sync_to_dev((h), &(script)[A_##symbol##_used[i]], 4); \
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DEBUG((" script, patching short field %s at %d to 0x%x\n", \
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#symbol, A_##symbol##_used[i], val)); \
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} \
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}
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static inline __u8
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NCR_700_readb(struct Scsi_Host *host, __u32 reg)
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{
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const struct NCR_700_Host_Parameters *hostdata
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= (struct NCR_700_Host_Parameters *)host->hostdata[0];
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return ioread8(hostdata->base + (reg^bE));
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}
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static inline __u32
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NCR_700_readl(struct Scsi_Host *host, __u32 reg)
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{
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const struct NCR_700_Host_Parameters *hostdata
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= (struct NCR_700_Host_Parameters *)host->hostdata[0];
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__u32 value = bEBus ? ioread32be(hostdata->base + reg) :
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ioread32(hostdata->base + reg);
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#if 1
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/* sanity check the register */
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BUG_ON((reg & 0x3) != 0);
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#endif
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return value;
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}
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static inline void
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NCR_700_writeb(__u8 value, struct Scsi_Host *host, __u32 reg)
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{
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const struct NCR_700_Host_Parameters *hostdata
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= (struct NCR_700_Host_Parameters *)host->hostdata[0];
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iowrite8(value, hostdata->base + (reg^bE));
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}
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static inline void
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NCR_700_writel(__u32 value, struct Scsi_Host *host, __u32 reg)
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{
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const struct NCR_700_Host_Parameters *hostdata
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= (struct NCR_700_Host_Parameters *)host->hostdata[0];
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#if 1
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/* sanity check the register */
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BUG_ON((reg & 0x3) != 0);
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#endif
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bEBus ? iowrite32be(value, hostdata->base + reg):
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iowrite32(value, hostdata->base + reg);
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}
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#endif
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