/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2020 Rockchip Electronics Co. Ltd.
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*
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* Author: Wyon Bi <bivvy.bi@rock-chips.com>
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*/
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#ifndef _RK628_H
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#define _RK628_H
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/regmap.h>
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#include <linux/version.h>
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#include <linux/of.h>
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#include <linux/wakelock.h>
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#include <linux/workqueue.h>
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#include <linux/regulator/consumer.h>
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#define DRIVER_VERSION "0.0.1"
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#define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l)))
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#define HIWORD_UPDATE(v, h, l) ((((v) << (l)) & GENMASK((h), (l))) | \
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(GENMASK((h), (l)) << 16))
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#define GRF_SYSTEM_CON0 0x0000
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#define SW_VSYNC_POL_MASK BIT(26)
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#define SW_VSYNC_POL(x) UPDATE(x, 26, 26)
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#define SW_HSYNC_POL_MASK BIT(25)
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#define SW_HSYNC_POL(x) UPDATE(x, 25, 25)
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#define SW_ADAPTER_I2CSLADR_MASK GENMASK(24, 22)
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#define SW_ADAPTER_I2CSLADR(x) UPDATE(x, 24, 22)
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#define SW_EDID_MODE_MASK BIT(21)
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#define SW_EDID_MODE(x) UPDATE(x, 21, 21)
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#define SW_I2S_DATA_OEN_MASK BIT(10)
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#define SW_I2S_DATA_OEN(x) UPDATE(x, 10, 10)
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#define SW_BT_DATA_OEN_MASK BIT(9)
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#define SW_BT_DATA_OEN BIT(9)
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#define SW_EFUSE_HDCP_EN_MASK BIT(8)
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#define SW_EFUSE_HDCP_EN(x) UPDATE(x, 8, 8)
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#define SW_OUTPUT_MODE_MASK GENMASK(7, 3)
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#define SW_OUTPUT_MODE(x) UPDATE(x, 7, 3)
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#define SW_INPUT_MODE_MASK GENMASK(2, 0)
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#define SW_INPUT_MODE(x) UPDATE(x, 2, 0)
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#define GRF_SYSTEM_CON1 0x0004
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#define GRF_SYSTEM_CON2 0x0008
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#define GRF_SYSTEM_CON3 0x000c
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#define GRF_GPIO_RX_CEC_SEL_MASK BIT(7)
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#define GRF_GPIO_RX_CEC_SEL(x) UPDATE(x, 7, 7)
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#define GRF_GPIO_RXDDC_SDA_SEL_MASK BIT(6)
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#define GRF_GPIO_RXDDC_SDA_SEL(x) UPDATE(x, 6, 6)
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#define GRF_GPIO_RXDDC_SCL_SEL_MASK BIT(5)
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#define GRF_GPIO_RXDDC_SCL_SEL(x) UPDATE(x, 5, 5)
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#define GRF_SCALER_CON0 0x0010
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#define SCL_VER_DOWN_MODE(x) HIWORD_UPDATE(x, 8, 8)
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#define SCL_HOR_DOWN_MODE(x) HIWORD_UPDATE(x, 7, 7)
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#define SCL_BIC_COE_SEL(x) HIWORD_UPDATE(x, 6, 5)
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#define SCL_VER_MODE(x) HIWORD_UPDATE(x, 4, 3)
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#define SCL_HOR_MODE(x) HIWORD_UPDATE(x, 2, 1)
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#define SCL_EN(x) HIWORD_UPDATE(x, 0, 0)
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#define GRF_SCALER_CON1 0x0014
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#define SCL_V_FACTOR(x) UPDATE(x, 31, 16)
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#define SCL_H_FACTOR(x) UPDATE(x, 15, 0)
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#define GRF_SCALER_CON2 0x0018
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#define DSP_FRAME_VST(x) UPDATE(x, 28, 16)
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#define DSP_FRAME_HST(x) UPDATE(x, 12, 0)
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#define GRF_SCALER_CON3 0x001c
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#define DSP_HS_END(x) UPDATE(x, 23, 16)
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#define DSP_HTOTAL(x) UPDATE(x, 12, 0)
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#define GRF_SCALER_CON4 0x0020
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#define DSP_HACT_ST(x) UPDATE(x, 28, 16)
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#define DSP_HACT_END(x) UPDATE(x, 12, 0)
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#define GRF_SCALER_CON5 0x0024
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#define DSP_VS_END(x) UPDATE(x, 23, 16)
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#define DSP_VTOTAL(x) UPDATE(x, 12, 0)
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#define GRF_SCALER_CON6 0x0028
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#define DSP_VACT_ST(x) UPDATE(x, 28, 16)
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#define DSP_VACT_END(x) UPDATE(x, 12, 0)
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#define GRF_SCALER_CON7 0x002c
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#define DSP_HBOR_ST(x) UPDATE(x, 28, 16)
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#define DSP_HBOR_END(x) UPDATE(x, 12, 0)
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#define GRF_SCALER_CON8 0x0030
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#define DSP_VBOR_ST(x) UPDATE(x, 28, 16)
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#define DSP_VBOR_END(x) UPDATE(x, 12, 0)
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#define GRF_POST_PROC_CON 0x0034
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#define SW_DCLK_OUT_INV_EN BIT(9)
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#define SW_DCLK_IN_INV_EN BIT(8)
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#define SW_TXPHY_REFCLK_SEL_MASK GENMASK(6, 5)
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#define SW_TXPHY_REFCLK_SEL(x) UPDATE(x, 6, 5)
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#define SW_HDMITX_VCLK_PLLREF_SEL_MASK BIT(4)
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#define SW_HDMITX_VCLK_PLLREF_SEL(x) UPDATE(x, 4, 4)
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#define SW_HDMITX_DCLK_INV_EN BIT(3)
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#define SW_SPLIT_MODE(x) UPDATE(x, 1, 1)
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#define SW_SPLIT_EN BIT(0)
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#define GRF_CSC_CTRL_CON 0x0038
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#define SW_YUV2VYU_SWP(x) HIWORD_UPDATE(x, 8, 8)
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#define SW_R2Y_EN(x) HIWORD_UPDATE(x, 4, 4)
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#define SW_Y2R_EN(x) HIWORD_UPDATE(x, 0, 0)
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#define GRF_LVDS_TX_CON 0x003c
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#define SW_LVDS_CON_DUAL_SEL(x) HIWORD_UPDATE(x, 12, 12)
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#define SW_LVDS_CON_DEN_POLARITY(x) HIWORD_UPDATE(x, 11, 11)
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#define SW_LVDS_CON_HS_POLARITY(x) HIWORD_UPDATE(x, 10, 10)
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#define SW_LVDS_CON_CLKINV(x) HIWORD_UPDATE(x, 9, 9)
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#define SW_LVDS_STARTPHASE(x) HIWORD_UPDATE(x, 8, 8)
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#define SW_LVDS_CON_STARTSEL(x) HIWORD_UPDATE(x, 7, 7)
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#define SW_LVDS_CON_CHASEL(x) HIWORD_UPDATE(x, 6, 6)
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#define SW_LVDS_TIE_VSYNC_VALUE(x) HIWORD_UPDATE(x, 5, 5)
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#define SW_LVDS_TIE_HSYNC_VALUE(x) HIWORD_UPDATE(x, 4, 4)
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#define SW_LVDS_TIE_DEN_ONLY(x) HIWORD_UPDATE(x, 3, 3)
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#define SW_LVDS_CON_MSBSEL(x) HIWORD_UPDATE(x, 2, 2)
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#define SW_LVDS_CON_SELECT(x) HIWORD_UPDATE(x, 1, 0)
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#define GRF_RGB_DEC_CON0 0x0040
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#define SW_HRES_MASK GENMASK(28, 16)
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#define SW_HRES(x) UPDATE(x, 28, 16)
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#define DUAL_DATA_SWAP BIT(6)
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#define DEC_DUALEDGE_EN BIT(5)
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#define SW_PROGRESS_EN BIT(4)
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#define SW_YC_SWAP BIT(3)
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#define SW_CAP_EN_ASYNC BIT(1)
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#define SW_CAP_EN_PSYNC BIT(0)
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#define GRF_RGB_DEC_CON1 0x0044
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#define SW_SET_X_MASK GENMASK(28, 16)
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#define SW_SET_X(x) HIWORD_UPDATE(x, 28, 16)
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#define SW_SET_Y_MASK GENMASK(28, 16)
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#define SW_SET_Y(x) HIWORD_UPDATE(x, 28, 16)
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#define GRF_RGB_DEC_CON2 0x0048
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#define GRF_RGB_ENC_CON 0x004c
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#define BT1120_UV_SWAP(x) HIWORD_UPDATE(x, 5, 5)
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#define ENC_DUALEDGE_EN(x) HIWORD_UPDATE(x, 3, 3)
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#define GRF_MIPI_LANE_DELAY_CON0 0x0050
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#define GRF_MIPI_LANE_DELAY_CON1 0x0054
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#define GRF_BT1120_DCLK_DELAY_CON0 0x0058
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#define GRF_BT1120_DCLK_DELAY_CON1 0x005c
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#define GRF_MIPI_TX0_CON 0x0060
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#define DPIUPDATECFG BIT(26)
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#define DPICOLORM BIT(25)
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#define DPISHUTDN BIT(24)
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#define CSI_PHYRSTZ BIT(21)
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#define CSI_PHYSHUTDOWNZ BIT(20)
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#define FORCETXSTOPMODE_MASK GENMASK(19, 16)
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#define FORCETXSTOPMODE(x) UPDATE(x, 19, 16)
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#define FORCERXMODE_MASK GENMASK(15, 12)
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#define FORCERXMODE(x) UPDATE(x, 15, 12)
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#define PHY_TESTCLR BIT(10)
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#define PHY_TESTCLK BIT(9)
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#define PHY_TESTEN BIT(8)
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#define PHY_TESTDIN_MASK GENMASK(7, 0)
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#define PHY_TESTDIN(x) UPDATE(x, 7, 0)
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#define GRF_DPHY0_STATUS 0x0064
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#define DPHY_PHYLOCK BIT(24)
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#define PHY_TESTDOUT_SHIFT 8
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#define GRF_MIPI_TX1_CON 0x0068
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#define GRF_DPHY1_STATUS 0x006c
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#define GRF_GPIO0AB_SEL_CON 0x0070
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#define GRF_GPIO1AB_SEL_CON 0x0074
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#define GRF_GPIO2AB_SEL_CON 0x0078
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#define GRF_GPIO2C_SEL_CON 0x007c
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#define GRF_GPIO3AB_SEL_CON 0x0080
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#define GRF_GPIO2A_SMT 0x0090
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#define GRF_GPIO2B_SMT 0x0094
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#define GRF_GPIO2C_SMT 0x0098
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#define GRF_GPIO3AB_SMT 0x009c
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#define GRF_GPIO0A_P_CON 0x00a0
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#define GRF_GPIO1A_P_CON 0x00a4
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#define GRF_GPIO2A_P_CON 0x00a8
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#define GRF_GPIO2B_P_CON 0x00ac
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#define GRF_GPIO2C_P_CON 0x00b0
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#define GRF_GPIO3A_P_CON 0x00b4
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#define GRF_GPIO3B_P_CON 0x00b8
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#define GRF_GPIO0B_D_CON 0x00c0
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#define GRF_GPIO1B_D_CON 0x00c4
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#define GRF_GPIO2A_D0_CON 0x00c8
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#define GRF_GPIO2A_D1_CON 0x00cc
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#define GRF_GPIO2B_D0_CON 0x00d0
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#define GRF_GPIO2B_D1_CON 0x00d4
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#define GRF_GPIO2C_D0_CON 0x00d8
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#define GRF_GPIO2C_D1_CON 0x00dc
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#define GRF_GPIO3A_D0_CON 0x00e0
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#define GRF_GPIO3A_D1_CON 0x00e4
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#define GRF_GPIO3B_D_CON 0x00e8
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#define GRF_GPIO_SR_CON 0x00ec
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#define GRF_INTR0_EN 0x0100
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#define GRF_INTR0_CLR_EN 0x0104
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#define GRF_INTR0_STATUS 0x0108
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#define GRF_INTR0_RAW_STATUS 0x010c
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#define GRF_INTR1_EN 0x0110
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#define GRF_INTR1_CLR_EN 0x0114
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#define GRF_INTR1_STATUS 0x0118
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#define GRF_INTR1_RAW_STATUS 0x011c
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#define GRF_SYSTEM_STATUS0 0x0120
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/* 0: i2c mode and mcu mode; 1: i2c mode only */
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#define I2C_ONLY_FLAG BIT(6)
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#define GRF_SYSTEM_STATUS3 0x012c
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#define GRF_SYSTEM_STATUS4 0x0130
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#define GRF_OS_REG0 0x0140
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#define GRF_OS_REG1 0x0144
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#define GRF_OS_REG2 0x0148
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#define GRF_OS_REG3 0x014c
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#define GRF_SOC_VERSION 0x0150
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#define GRF_MAX_REGISTER GRF_SOC_VERSION
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#define DRM_MODE_FLAG_PHSYNC (1<<0)
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#define DRM_MODE_FLAG_NHSYNC (1<<1)
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#define DRM_MODE_FLAG_PVSYNC (1<<2)
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#define DRM_MODE_FLAG_NVSYNC (1<<3)
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enum {
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COMBTXPHY_MODULEA_EN = BIT(0),
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COMBTXPHY_MODULEB_EN = BIT(1),
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};
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enum {
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RK628_DEV_GRF,
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RK628_DEV_COMBRXPHY,
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RK628_DEV_HDMIRX = 3,
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RK628_DEV_CSI,
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RK628_DEV_DSI0,
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RK628_DEV_DSI1,
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RK628_DEV_HDMITX,
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RK628_DEV_GVI,
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RK628_DEV_COMBTXPHY,
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RK628_DEV_ADAPTER,
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RK628_DEV_EFUSE,
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RK628_DEV_CRU,
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RK628_DEV_GPIO0,
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RK628_DEV_GPIO1,
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RK628_DEV_GPIO2,
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RK628_DEV_GPIO3,
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RK628_DEV_MAX,
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};
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enum rk628_input_mode {
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INPUT_MODE_HDMI,
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INPUT_MODE_BT1120 = 2,
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INPUT_MODE_RGB,
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INPUT_MODE_YUV,
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};
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enum rk628_output_mode {
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OUTPUT_MODE_GVI = 1,
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OUTPUT_MODE_LVDS,
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OUTPUT_MODE_HDMI,
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OUTPUT_MODE_CSI,
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OUTPUT_MODE_DSI,
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OUTPUT_MODE_BT1120 = 8,
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OUTPUT_MODE_RGB = 16,
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OUTPUT_MODE_YUV = 24,
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};
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enum phy_mode {
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PHY_MODE_INVALID,
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PHY_MODE_VIDEO_MIPI,
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PHY_MODE_VIDEO_LVDS,
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PHY_MODE_VIDEO_GVI,
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};
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enum lvds_format {
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LVDS_FORMAT_VESA_24BIT,
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LVDS_FORMAT_JEIDA_24BIT,
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LVDS_FORMAT_JEIDA_18BIT,
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LVDS_FORMAT_VESA_18BIT,
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};
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enum lvds_link_type {
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LVDS_SINGLE_LINK,
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LVDS_DUAL_LINK_ODD_EVEN_PIXELS,
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LVDS_DUAL_LINK_EVEN_ODD_PIXELS,
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LVDS_DUAL_LINK_LEFT_RIGHT_PIXELS,
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LVDS_DUAL_LINK_RIGHT_LEFT_PIXELS,
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};
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enum gvi_color_depth {
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COLOR_DEPTH_RGB_YUV444_18BIT,
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COLOR_DEPTH_RGB_YUV444_24BIT,
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COLOR_DEPTH_RGB_YUV444_30BIT,
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COLOR_DEPTH_YUV422_16BIT = 8,
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COLOR_DEPTH_YUV422_20BIT,
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};
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enum dsi_mode_flags {
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MIPI_DSI_MODE_VIDEO = 1,
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MIPI_DSI_MODE_VIDEO_BURST = 2,
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MIPI_DSI_MODE_VIDEO_SYNC_PULSE = 4,
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MIPI_DSI_MODE_VIDEO_HFP = 8,
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MIPI_DSI_MODE_VIDEO_HBP = 16,
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MIPI_DSI_MODE_EOT_PACKET = 32,
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MIPI_DSI_CLOCK_NON_CONTINUOUS = 64,
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MIPI_DSI_MODE_LPM = 128,
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};
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enum dsi_bus_format {
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MIPI_DSI_FMT_RGB888,
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MIPI_DSI_FMT_RGB666,
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MIPI_DSI_FMT_RGB666_PACKED,
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MIPI_DSI_FMT_RGB565,
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};
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enum gvi_bus_format {
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GVI_MEDIA_BUS_FMT_RGB666_1X18 = 9,
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GVI_MEDIA_BUS_FMT_RGB888_1X24 = 10,
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GVI_MEDIA_BUS_FMT_YUYV10_1X20 = 13,
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GVI_MEDIA_BUS_FMT_YUYV8_1X16 = 17,
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GVI_MEDIA_BUS_FMT_RGB101010_1X30 = 24,
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};
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enum bus_format {
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BUS_FMT_RGB = 0,
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BUS_FMT_YUV422 = 1,
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BUS_FMT_YUV444 = 2,
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BUS_FMT_YUV420 = 3,
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BUS_FMT_UNKNOWN,
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};
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enum rk628_mode_sync_pol {
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MODE_FLAG_NSYNC,
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MODE_FLAG_PSYNC,
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};
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#undef BT1120_DUAL_EDGE
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struct rk628_videomode {
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u32 pixelclock; /* pixelclock in Hz */
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u32 hactive;
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u32 hfront_porch;
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u32 hback_porch;
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u32 hsync_len;
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u32 vactive;
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u32 vfront_porch;
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u32 vback_porch;
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u32 vsync_len;
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unsigned int flags; /* display flags */
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};
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struct rk628_display_mode {
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int clock; /* in kHz */
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int hdisplay;
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int hsync_start;
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int hsync_end;
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int htotal;
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int vdisplay;
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int vsync_start;
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int vsync_end;
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int vtotal;
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unsigned int flags;
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};
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struct cmd_ctrl_hdr {
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u8 dtype; /* data type */
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u8 wait; /* ms */
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u8 dlen; /* payload len */
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} __packed;
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struct cmd_desc {
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struct cmd_ctrl_hdr dchdr;
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u8 *payload;
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};
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struct panel_cmds {
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u8 *buf;
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int blen;
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struct cmd_desc *cmds;
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int cmd_cnt;
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};
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struct panel_simple {
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struct backlight_device *backlight;
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struct regulator *supply;
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struct gpio_desc *enable_gpio;
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struct gpio_desc *reset_gpio;
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struct panel_cmds *on_cmds;
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struct panel_cmds *off_cmds;
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};
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struct rk628_dsi {
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int bpp; /* 24/18/16*/
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enum dsi_bus_format bus_format;
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enum dsi_mode_flags mode_flags;
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bool slave;
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bool master;
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uint8_t channel;
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uint8_t lanes;
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uint8_t id; /* 0:dsi0 1:dsi1 */
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struct rk628 *rk628;
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};
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struct rk628_lvds {
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enum lvds_format format;
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enum lvds_link_type link_type;
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};
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struct rk628_gvi {
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enum gvi_bus_format bus_format;
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enum gvi_color_depth color_depth;
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uint8_t lanes;
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bool division_mode;
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bool frm_rst;
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u8 byte_mode;
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};
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struct rk628_combtxphy {
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enum phy_mode mode;
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unsigned int flags;
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u8 ref_div;
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u8 fb_div;
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u16 frac_div;
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u8 rate_div;
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u32 bus_width;
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bool division_mode;
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};
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struct rk628 {
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struct device *dev;
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struct i2c_client *client;
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struct regmap *regmap[RK628_DEV_MAX];
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struct gpio_desc *reset_gpio;
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struct gpio_desc *enable_gpio;
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struct gpio_desc *plugin_det_gpio;
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int plugin_irq;
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int hdmirx_irq;
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struct clk *soc_24M;
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struct workqueue_struct *monitor_wq;
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struct delayed_work delay_work;
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struct workqueue_struct *dsi_wq;
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struct delayed_work dsi_delay_work;
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struct panel_simple *panel;
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void *hdmirx;
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bool display_enabled;
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enum rk628_input_mode input_mode;
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enum rk628_output_mode output_mode;
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struct rk628_display_mode src_mode;
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struct rk628_display_mode dst_mode;
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enum bus_format input_fmt;
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enum bus_format output_fmt;
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struct rk628_dsi dsi0;
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struct rk628_dsi dsi1;
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struct rk628_lvds lvds;
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struct rk628_gvi gvi;
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struct rk628_combtxphy combtxphy;
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int sync_pol;
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void *csi;
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};
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static inline int rk628_i2c_write(struct rk628 *rk628, u32 reg, u32 val)
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{
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int region = (reg >> 16) & 0xff;
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int ret = 0;
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ret = regmap_write(rk628->regmap[region], reg, val);
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if (ret < 0)
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pr_info("%s: i2c err reg=0x%x, val=0x%x, ret=%d\n", __func__, reg, val, ret);
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return ret;
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}
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static inline int rk628_i2c_read(struct rk628 *rk628, u32 reg, u32 *val)
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{
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int region = (reg >> 16) & 0xff;
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int ret = 0;
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ret = regmap_read(rk628->regmap[region], reg, val);
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if (ret < 0)
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pr_info("%s: i2c err reg=0x%x, val=0x%x ret=%d\n", __func__, reg, *val, ret);
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return ret;
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}
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static inline int rk628_i2c_update_bits(struct rk628 *rk628, u32 reg, u32 mask,
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u32 val)
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{
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int region = (reg >> 16) & 0xff;
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return regmap_update_bits(rk628->regmap[region], reg, mask, val);
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}
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#include "rk628_grf.h"
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#include "rk628_gpio.h"
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#include "rk628_pinctrl.h"
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#endif
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