// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Rockchip Successive Approximation Register (SAR) A/D Converter
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* Copyright (C) 2014 ROCKCHIP, Inc.
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/clk.h>
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#include <linux/completion.h>
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#include <linux/delay.h>
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#include <linux/reset.h>
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#include <linux/regulator/consumer.h>
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#include <linux/iio/buffer.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/trigger_consumer.h>
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#include <linux/iio/triggered_buffer.h>
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#define SARADC_DATA 0x00
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#define SARADC_STAS 0x04
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#define SARADC_STAS_BUSY BIT(0)
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#define SARADC_CTRL 0x08
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#define SARADC_CTRL_IRQ_STATUS BIT(6)
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#define SARADC_CTRL_IRQ_ENABLE BIT(5)
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#define SARADC_CTRL_POWER_CTRL BIT(3)
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#define SARADC_CTRL_CHN_MASK 0x7
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#define SARADC_DLY_PU_SOC 0x0c
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#define SARADC_DLY_PU_SOC_MASK 0x3f
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#define SARADC_TIMEOUT msecs_to_jiffies(100)
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#define SARADC_MAX_CHANNELS 8
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/* v2 registers */
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#define SARADC2_CONV_CON 0x0
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#define SARADC_T_PD_SOC 0x4
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#define SARADC_T_DAS_SOC 0xc
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#define SARADC2_END_INT_EN 0x104
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#define SARADC2_ST_CON 0x108
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#define SARADC2_STATUS 0x10c
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#define SARADC2_END_INT_ST 0x110
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#define SARADC2_DATA_BASE 0x120
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#define SARADC2_EN_END_INT BIT(0)
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#define SARADC2_START BIT(4)
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#define SARADC2_SINGLE_MODE BIT(5)
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struct rockchip_saradc;
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struct rockchip_saradc_data {
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const struct iio_chan_spec *channels;
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int num_channels;
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unsigned long clk_rate;
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void (*start)(struct rockchip_saradc *info, int chn);
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int (*read)(struct rockchip_saradc *info);
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void (*power_down)(struct rockchip_saradc *info);
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};
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struct rockchip_saradc {
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void __iomem *regs;
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struct clk *pclk;
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struct clk *clk;
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struct completion completion;
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struct regulator *vref;
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int uv_vref;
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struct reset_control *reset;
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const struct rockchip_saradc_data *data;
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u16 last_val;
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const struct iio_chan_spec *last_chan;
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struct notifier_block nb;
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bool suspended;
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#ifdef CONFIG_ROCKCHIP_SARADC_TEST_CHN
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bool test;
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u32 chn;
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spinlock_t lock;
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struct workqueue_struct *wq;
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struct delayed_work work;
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#endif
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};
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static void rockchip_saradc_reset_controller(struct reset_control *reset);
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static void rockchip_saradc_start_v1(struct rockchip_saradc *info,
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int chn)
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{
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/* 8 clock periods as delay between power up and start cmd */
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writel_relaxed(8, info->regs + SARADC_DLY_PU_SOC);
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/* Select the channel to be used and trigger conversion */
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writel(SARADC_CTRL_POWER_CTRL | (chn & SARADC_CTRL_CHN_MASK) |
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SARADC_CTRL_IRQ_ENABLE, info->regs + SARADC_CTRL);
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}
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static void rockchip_saradc_start_v2(struct rockchip_saradc *info,
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int chn)
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{
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int val;
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/* If read other chn at anytime, then chn1 will error, assert
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* controller as a workaround.
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*/
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if (info->reset)
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rockchip_saradc_reset_controller(info->reset);
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writel_relaxed(0xc, info->regs + SARADC_T_DAS_SOC);
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writel_relaxed(0x20, info->regs + SARADC_T_PD_SOC);
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val = SARADC2_EN_END_INT << 16 | SARADC2_EN_END_INT;
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writel_relaxed(val, info->regs + SARADC2_END_INT_EN);
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val = SARADC2_START | SARADC2_SINGLE_MODE | chn;
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writel(val << 16 | val, info->regs + SARADC2_CONV_CON);
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}
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static void rockchip_saradc_start(struct rockchip_saradc *info,
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int chn)
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{
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info->data->start(info, chn);
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}
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static int rockchip_saradc_read_v1(struct rockchip_saradc *info)
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{
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return readl_relaxed(info->regs + SARADC_DATA);
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}
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static int rockchip_saradc_read_v2(struct rockchip_saradc *info)
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{
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int offset;
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int channel;
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/* Clear irq */
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writel_relaxed(0x1, info->regs + SARADC2_END_INT_ST);
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#ifdef CONFIG_ROCKCHIP_SARADC_TEST_CHN
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channel = info->chn;
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#else
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channel = info->last_chan->channel;
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#endif
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offset = SARADC2_DATA_BASE + channel * 0x4;
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return readl_relaxed(info->regs + offset);
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}
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static int rockchip_saradc_read(struct rockchip_saradc *info)
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{
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return info->data->read(info);
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}
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static void rockchip_saradc_power_down_v1(struct rockchip_saradc *info)
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{
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writel_relaxed(0, info->regs + SARADC_CTRL);
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}
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static void rockchip_saradc_power_down(struct rockchip_saradc *info)
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{
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if (info->data->power_down)
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info->data->power_down(info);
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}
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static int rockchip_saradc_conversion(struct rockchip_saradc *info,
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struct iio_chan_spec const *chan)
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{
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reinit_completion(&info->completion);
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/* prevent isr get NULL last_chan */
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info->last_chan = chan;
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rockchip_saradc_start(info, chan->channel);
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if (!wait_for_completion_timeout(&info->completion, SARADC_TIMEOUT))
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return -ETIMEDOUT;
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return 0;
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}
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static int rockchip_saradc_read_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int *val, int *val2, long mask)
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{
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struct rockchip_saradc *info = iio_priv(indio_dev);
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int ret;
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#ifdef CONFIG_ROCKCHIP_SARADC_TEST_CHN
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if (info->test)
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return 0;
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#endif
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switch (mask) {
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case IIO_CHAN_INFO_RAW:
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mutex_lock(&indio_dev->mlock);
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if (info->suspended) {
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mutex_unlock(&indio_dev->mlock);
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return -EBUSY;
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}
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ret = rockchip_saradc_conversion(info, chan);
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if (ret) {
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rockchip_saradc_power_down(info);
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mutex_unlock(&indio_dev->mlock);
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return ret;
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}
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*val = info->last_val;
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mutex_unlock(&indio_dev->mlock);
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return IIO_VAL_INT;
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case IIO_CHAN_INFO_SCALE:
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/* It is a dummy regulator */
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if (info->uv_vref < 0)
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return info->uv_vref;
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*val = info->uv_vref / 1000;
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*val2 = chan->scan_type.realbits;
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return IIO_VAL_FRACTIONAL_LOG2;
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default:
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return -EINVAL;
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}
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}
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static irqreturn_t rockchip_saradc_isr(int irq, void *dev_id)
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{
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struct rockchip_saradc *info = dev_id;
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#ifdef CONFIG_ROCKCHIP_SARADC_TEST_CHN
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unsigned long flags;
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#endif
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/* Read value */
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info->last_val = rockchip_saradc_read(info);
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#ifndef CONFIG_ROCKCHIP_SARADC_TEST_CHN
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info->last_val &= GENMASK(info->last_chan->scan_type.realbits - 1, 0);
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#endif
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rockchip_saradc_power_down(info);
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complete(&info->completion);
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#ifdef CONFIG_ROCKCHIP_SARADC_TEST_CHN
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spin_lock_irqsave(&info->lock, flags);
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if (info->test) {
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pr_info("chn[%d] val = %d\n", info->chn, info->last_val);
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mod_delayed_work(info->wq, &info->work, msecs_to_jiffies(100));
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}
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spin_unlock_irqrestore(&info->lock, flags);
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#endif
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return IRQ_HANDLED;
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}
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static const struct iio_info rockchip_saradc_iio_info = {
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.read_raw = rockchip_saradc_read_raw,
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};
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#define SARADC_CHANNEL(_index, _id, _res) { \
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.type = IIO_VOLTAGE, \
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.indexed = 1, \
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.channel = _index, \
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
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.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
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.datasheet_name = _id, \
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.scan_index = _index, \
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.scan_type = { \
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.sign = 'u', \
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.realbits = _res, \
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.storagebits = 16, \
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.endianness = IIO_CPU, \
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}, \
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}
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static const struct iio_chan_spec rockchip_saradc_iio_channels[] = {
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SARADC_CHANNEL(0, "adc0", 10),
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SARADC_CHANNEL(1, "adc1", 10),
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SARADC_CHANNEL(2, "adc2", 10),
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};
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static const struct rockchip_saradc_data saradc_data = {
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.channels = rockchip_saradc_iio_channels,
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.num_channels = ARRAY_SIZE(rockchip_saradc_iio_channels),
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.clk_rate = 1000000,
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.start = rockchip_saradc_start_v1,
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.read = rockchip_saradc_read_v1,
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.power_down = rockchip_saradc_power_down_v1,
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};
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static const struct iio_chan_spec rockchip_rk3066_tsadc_iio_channels[] = {
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SARADC_CHANNEL(0, "adc0", 12),
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SARADC_CHANNEL(1, "adc1", 12),
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};
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static const struct rockchip_saradc_data rk3066_tsadc_data = {
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.channels = rockchip_rk3066_tsadc_iio_channels,
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.num_channels = ARRAY_SIZE(rockchip_rk3066_tsadc_iio_channels),
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.clk_rate = 50000,
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.start = rockchip_saradc_start_v1,
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.read = rockchip_saradc_read_v1,
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.power_down = rockchip_saradc_power_down_v1,
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};
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static const struct iio_chan_spec rockchip_rk3399_saradc_iio_channels[] = {
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SARADC_CHANNEL(0, "adc0", 10),
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SARADC_CHANNEL(1, "adc1", 10),
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SARADC_CHANNEL(2, "adc2", 10),
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SARADC_CHANNEL(3, "adc3", 10),
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SARADC_CHANNEL(4, "adc4", 10),
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SARADC_CHANNEL(5, "adc5", 10),
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};
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static const struct rockchip_saradc_data rk3399_saradc_data = {
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.channels = rockchip_rk3399_saradc_iio_channels,
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.num_channels = ARRAY_SIZE(rockchip_rk3399_saradc_iio_channels),
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.clk_rate = 1000000,
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.start = rockchip_saradc_start_v1,
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.read = rockchip_saradc_read_v1,
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.power_down = rockchip_saradc_power_down_v1,
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};
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static const struct iio_chan_spec rockchip_rk3528_saradc_iio_channels[] = {
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SARADC_CHANNEL(0, "adc0", 10),
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SARADC_CHANNEL(1, "adc1", 10),
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SARADC_CHANNEL(2, "adc2", 10),
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SARADC_CHANNEL(3, "adc3", 10),
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};
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static const struct rockchip_saradc_data rk3528_saradc_data = {
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.channels = rockchip_rk3528_saradc_iio_channels,
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.num_channels = ARRAY_SIZE(rockchip_rk3528_saradc_iio_channels),
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.clk_rate = 1000000,
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.start = rockchip_saradc_start_v2,
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.read = rockchip_saradc_read_v2,
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};
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static const struct iio_chan_spec rockchip_rk3562_saradc_iio_channels[] = {
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SARADC_CHANNEL(0, "adc0", 10),
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SARADC_CHANNEL(1, "adc1", 10),
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SARADC_CHANNEL(2, "adc2", 10),
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SARADC_CHANNEL(3, "adc3", 10),
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SARADC_CHANNEL(4, "adc4", 10),
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SARADC_CHANNEL(5, "adc5", 10),
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SARADC_CHANNEL(6, "adc6", 10),
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SARADC_CHANNEL(7, "adc7", 10),
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};
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static const struct rockchip_saradc_data rk3562_saradc_data = {
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.channels = rockchip_rk3562_saradc_iio_channels,
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.num_channels = ARRAY_SIZE(rockchip_rk3562_saradc_iio_channels),
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.clk_rate = 1000000,
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.start = rockchip_saradc_start_v2,
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.read = rockchip_saradc_read_v2,
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};
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static const struct iio_chan_spec rockchip_rk3568_saradc_iio_channels[] = {
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SARADC_CHANNEL(0, "adc0", 10),
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SARADC_CHANNEL(1, "adc1", 10),
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SARADC_CHANNEL(2, "adc2", 10),
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SARADC_CHANNEL(3, "adc3", 10),
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SARADC_CHANNEL(4, "adc4", 10),
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SARADC_CHANNEL(5, "adc5", 10),
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SARADC_CHANNEL(6, "adc6", 10),
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SARADC_CHANNEL(7, "adc7", 10),
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};
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static const struct rockchip_saradc_data rk3568_saradc_data = {
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.channels = rockchip_rk3568_saradc_iio_channels,
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.num_channels = ARRAY_SIZE(rockchip_rk3568_saradc_iio_channels),
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.clk_rate = 1000000,
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.start = rockchip_saradc_start_v1,
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.read = rockchip_saradc_read_v1,
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.power_down = rockchip_saradc_power_down_v1,
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};
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static const struct iio_chan_spec rockchip_rk3588_saradc_iio_channels[] = {
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SARADC_CHANNEL(0, "adc0", 12),
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SARADC_CHANNEL(1, "adc1", 12),
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SARADC_CHANNEL(2, "adc2", 12),
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SARADC_CHANNEL(3, "adc3", 12),
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SARADC_CHANNEL(4, "adc4", 12),
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SARADC_CHANNEL(5, "adc5", 12),
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SARADC_CHANNEL(6, "adc6", 12),
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SARADC_CHANNEL(7, "adc7", 12),
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};
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static const struct rockchip_saradc_data rk3588_saradc_data = {
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.channels = rockchip_rk3588_saradc_iio_channels,
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.num_channels = ARRAY_SIZE(rockchip_rk3588_saradc_iio_channels),
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.clk_rate = 1000000,
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.start = rockchip_saradc_start_v2,
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.read = rockchip_saradc_read_v2,
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};
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static const struct iio_chan_spec rockchip_rv1106_saradc_iio_channels[] = {
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SARADC_CHANNEL(0, "adc0", 10),
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SARADC_CHANNEL(1, "adc1", 10),
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};
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static const struct rockchip_saradc_data rv1106_saradc_data = {
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.channels = rockchip_rv1106_saradc_iio_channels,
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.num_channels = ARRAY_SIZE(rockchip_rv1106_saradc_iio_channels),
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.clk_rate = 1000000,
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.start = rockchip_saradc_start_v2,
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.read = rockchip_saradc_read_v2,
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};
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static const struct of_device_id rockchip_saradc_match[] = {
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{
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.compatible = "rockchip,saradc",
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.data = &saradc_data,
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}, {
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.compatible = "rockchip,rk3066-tsadc",
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.data = &rk3066_tsadc_data,
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}, {
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.compatible = "rockchip,rk3399-saradc",
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.data = &rk3399_saradc_data,
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}, {
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.compatible = "rockchip,rk3528-saradc",
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.data = &rk3528_saradc_data,
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}, {
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.compatible = "rockchip,rk3562-saradc",
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.data = &rk3562_saradc_data,
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}, {
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.compatible = "rockchip,rk3568-saradc",
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.data = &rk3568_saradc_data,
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}, {
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.compatible = "rockchip,rk3588-saradc",
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.data = &rk3588_saradc_data,
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}, {
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.compatible = "rockchip,rv1106-saradc",
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.data = &rv1106_saradc_data,
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},
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{},
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};
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MODULE_DEVICE_TABLE(of, rockchip_saradc_match);
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/*
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* Reset SARADC Controller.
|
*/
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static void rockchip_saradc_reset_controller(struct reset_control *reset)
|
{
|
reset_control_assert(reset);
|
usleep_range(10, 20);
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reset_control_deassert(reset);
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}
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static void rockchip_saradc_clk_disable(void *data)
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{
|
struct rockchip_saradc *info = data;
|
|
clk_disable_unprepare(info->clk);
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}
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|
static void rockchip_saradc_pclk_disable(void *data)
|
{
|
struct rockchip_saradc *info = data;
|
|
clk_disable_unprepare(info->pclk);
|
}
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|
static void rockchip_saradc_regulator_disable(void *data)
|
{
|
struct rockchip_saradc *info = data;
|
|
regulator_disable(info->vref);
|
}
|
|
static irqreturn_t rockchip_saradc_trigger_handler(int irq, void *p)
|
{
|
struct iio_poll_func *pf = p;
|
struct iio_dev *i_dev = pf->indio_dev;
|
struct rockchip_saradc *info = iio_priv(i_dev);
|
/*
|
* @values: each channel takes an u16 value
|
* @timestamp: will be 8-byte aligned automatically
|
*/
|
struct {
|
u16 values[SARADC_MAX_CHANNELS];
|
int64_t timestamp;
|
} data;
|
int ret;
|
int i, j = 0;
|
|
mutex_lock(&i_dev->mlock);
|
|
for_each_set_bit(i, i_dev->active_scan_mask, i_dev->masklength) {
|
const struct iio_chan_spec *chan = &i_dev->channels[i];
|
|
ret = rockchip_saradc_conversion(info, chan);
|
if (ret) {
|
rockchip_saradc_power_down(info);
|
goto out;
|
}
|
|
data.values[j] = info->last_val;
|
j++;
|
}
|
|
iio_push_to_buffers_with_timestamp(i_dev, &data, iio_get_time_ns(i_dev));
|
out:
|
mutex_unlock(&i_dev->mlock);
|
|
iio_trigger_notify_done(i_dev->trig);
|
|
return IRQ_HANDLED;
|
}
|
|
static int rockchip_saradc_volt_notify(struct notifier_block *nb,
|
unsigned long event,
|
void *data)
|
{
|
struct rockchip_saradc *info =
|
container_of(nb, struct rockchip_saradc, nb);
|
|
if (event & REGULATOR_EVENT_VOLTAGE_CHANGE)
|
info->uv_vref = (unsigned long)data;
|
|
return NOTIFY_OK;
|
}
|
|
static void rockchip_saradc_regulator_unreg_notifier(void *data)
|
{
|
struct rockchip_saradc *info = data;
|
|
regulator_unregister_notifier(info->vref, &info->nb);
|
}
|
|
#ifdef CONFIG_ROCKCHIP_SARADC_TEST_CHN
|
static ssize_t saradc_test_chn_store(struct device *dev,
|
struct device_attribute *attr,
|
const char *buf, size_t size)
|
{
|
u32 val = 0;
|
int err;
|
struct iio_dev *indio_dev = dev_get_drvdata(dev);
|
struct rockchip_saradc *info = iio_priv(indio_dev);
|
unsigned long flags;
|
|
err = kstrtou32(buf, 10, &val);
|
if (err)
|
return err;
|
|
spin_lock_irqsave(&info->lock, flags);
|
|
if (val > SARADC_CTRL_CHN_MASK && info->test) {
|
info->test = false;
|
spin_unlock_irqrestore(&info->lock, flags);
|
cancel_delayed_work_sync(&info->work);
|
return size;
|
}
|
|
if (!info->test && val <= SARADC_CTRL_CHN_MASK) {
|
info->test = true;
|
info->chn = val;
|
mod_delayed_work(info->wq, &info->work, msecs_to_jiffies(100));
|
}
|
|
spin_unlock_irqrestore(&info->lock, flags);
|
|
return size;
|
}
|
|
static DEVICE_ATTR_WO(saradc_test_chn);
|
|
static struct attribute *saradc_attrs[] = {
|
&dev_attr_saradc_test_chn.attr,
|
NULL
|
};
|
|
static const struct attribute_group rockchip_saradc_attr_group = {
|
.attrs = saradc_attrs,
|
};
|
|
static void rockchip_saradc_remove_sysgroup(void *data)
|
{
|
struct platform_device *pdev = data;
|
|
sysfs_remove_group(&pdev->dev.kobj, &rockchip_saradc_attr_group);
|
}
|
|
static void rockchip_saradc_destroy_wq(void *data)
|
{
|
struct rockchip_saradc *info = data;
|
|
destroy_workqueue(info->wq);
|
}
|
|
static void rockchip_saradc_test_work(struct work_struct *work)
|
{
|
struct rockchip_saradc *info = container_of(work,
|
struct rockchip_saradc, work.work);
|
|
rockchip_saradc_start(info, info->chn);
|
}
|
#endif
|
|
static int rockchip_saradc_probe(struct platform_device *pdev)
|
{
|
struct rockchip_saradc *info = NULL;
|
struct device_node *np = pdev->dev.of_node;
|
struct iio_dev *indio_dev = NULL;
|
struct resource *mem;
|
const struct of_device_id *match;
|
int ret;
|
int irq;
|
|
if (!np)
|
return -ENODEV;
|
|
indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*info));
|
if (!indio_dev) {
|
dev_err(&pdev->dev, "failed allocating iio device\n");
|
return -ENOMEM;
|
}
|
info = iio_priv(indio_dev);
|
|
match = of_match_device(rockchip_saradc_match, &pdev->dev);
|
if (!match) {
|
dev_err(&pdev->dev, "failed to match device\n");
|
return -ENODEV;
|
}
|
|
info->data = match->data;
|
|
/* Sanity check for possible later IP variants with more channels */
|
if (info->data->num_channels > SARADC_MAX_CHANNELS) {
|
dev_err(&pdev->dev, "max channels exceeded");
|
return -EINVAL;
|
}
|
|
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
info->regs = devm_ioremap_resource(&pdev->dev, mem);
|
if (IS_ERR(info->regs))
|
return PTR_ERR(info->regs);
|
|
/*
|
* The reset should be an optional property, as it should work
|
* with old devicetrees as well
|
*/
|
info->reset = devm_reset_control_get_exclusive(&pdev->dev,
|
"saradc-apb");
|
if (IS_ERR(info->reset)) {
|
ret = PTR_ERR(info->reset);
|
if (ret != -ENOENT)
|
return ret;
|
|
dev_dbg(&pdev->dev, "no reset control found\n");
|
info->reset = NULL;
|
}
|
|
init_completion(&info->completion);
|
|
irq = platform_get_irq(pdev, 0);
|
if (irq < 0)
|
return irq;
|
|
ret = devm_request_irq(&pdev->dev, irq, rockchip_saradc_isr,
|
0, dev_name(&pdev->dev), info);
|
if (ret < 0) {
|
dev_err(&pdev->dev, "failed requesting irq %d\n", irq);
|
return ret;
|
}
|
|
info->pclk = devm_clk_get(&pdev->dev, "apb_pclk");
|
if (IS_ERR(info->pclk)) {
|
dev_err(&pdev->dev, "failed to get pclk\n");
|
return PTR_ERR(info->pclk);
|
}
|
|
info->clk = devm_clk_get(&pdev->dev, "saradc");
|
if (IS_ERR(info->clk)) {
|
dev_err(&pdev->dev, "failed to get adc clock\n");
|
return PTR_ERR(info->clk);
|
}
|
|
info->vref = devm_regulator_get(&pdev->dev, "vref");
|
if (IS_ERR(info->vref)) {
|
dev_err(&pdev->dev, "failed to get regulator, %ld\n",
|
PTR_ERR(info->vref));
|
return PTR_ERR(info->vref);
|
}
|
|
if (info->reset)
|
rockchip_saradc_reset_controller(info->reset);
|
|
/*
|
* Use a default value for the converter clock.
|
* This may become user-configurable in the future.
|
*/
|
ret = clk_set_rate(info->clk, info->data->clk_rate);
|
if (ret < 0) {
|
dev_err(&pdev->dev, "failed to set adc clk rate, %d\n", ret);
|
return ret;
|
}
|
|
ret = regulator_enable(info->vref);
|
if (ret < 0) {
|
dev_err(&pdev->dev, "failed to enable vref regulator\n");
|
return ret;
|
}
|
ret = devm_add_action_or_reset(&pdev->dev,
|
rockchip_saradc_regulator_disable, info);
|
if (ret) {
|
dev_err(&pdev->dev, "failed to register devm action, %d\n",
|
ret);
|
return ret;
|
}
|
|
ret = regulator_get_voltage(info->vref);
|
if (ret < 0) {
|
dev_err(&pdev->dev, "failed to get voltage\n");
|
return ret;
|
}
|
|
info->uv_vref = ret;
|
|
ret = clk_prepare_enable(info->pclk);
|
if (ret < 0) {
|
dev_err(&pdev->dev, "failed to enable pclk\n");
|
return ret;
|
}
|
ret = devm_add_action_or_reset(&pdev->dev,
|
rockchip_saradc_pclk_disable, info);
|
if (ret) {
|
dev_err(&pdev->dev, "failed to register devm action, %d\n",
|
ret);
|
return ret;
|
}
|
|
ret = clk_prepare_enable(info->clk);
|
if (ret < 0) {
|
dev_err(&pdev->dev, "failed to enable converter clock\n");
|
return ret;
|
}
|
ret = devm_add_action_or_reset(&pdev->dev,
|
rockchip_saradc_clk_disable, info);
|
if (ret) {
|
dev_err(&pdev->dev, "failed to register devm action, %d\n",
|
ret);
|
return ret;
|
}
|
|
platform_set_drvdata(pdev, indio_dev);
|
|
indio_dev->name = dev_name(&pdev->dev);
|
indio_dev->info = &rockchip_saradc_iio_info;
|
indio_dev->modes = INDIO_DIRECT_MODE;
|
|
indio_dev->channels = info->data->channels;
|
indio_dev->num_channels = info->data->num_channels;
|
ret = devm_iio_triggered_buffer_setup(&indio_dev->dev, indio_dev, NULL,
|
rockchip_saradc_trigger_handler,
|
NULL);
|
if (ret)
|
return ret;
|
|
info->nb.notifier_call = rockchip_saradc_volt_notify;
|
ret = regulator_register_notifier(info->vref, &info->nb);
|
if (ret)
|
return ret;
|
|
ret = devm_add_action_or_reset(&pdev->dev,
|
rockchip_saradc_regulator_unreg_notifier,
|
info);
|
if (ret)
|
return ret;
|
|
#ifdef CONFIG_ROCKCHIP_SARADC_TEST_CHN
|
info->wq = create_singlethread_workqueue("adc_wq");
|
INIT_DELAYED_WORK(&info->work, rockchip_saradc_test_work);
|
spin_lock_init(&info->lock);
|
ret = sysfs_create_group(&pdev->dev.kobj, &rockchip_saradc_attr_group);
|
if (ret)
|
return ret;
|
|
ret = devm_add_action_or_reset(&pdev->dev,
|
rockchip_saradc_remove_sysgroup, pdev);
|
if (ret) {
|
dev_err(&pdev->dev, "failed to register devm action, %d\n",
|
ret);
|
return ret;
|
}
|
|
ret = devm_add_action_or_reset(&pdev->dev,
|
rockchip_saradc_destroy_wq, info);
|
if (ret) {
|
dev_err(&pdev->dev, "failed to register destroy_wq, %d\n",
|
ret);
|
return ret;
|
}
|
#endif
|
return devm_iio_device_register(&pdev->dev, indio_dev);
|
}
|
|
#ifdef CONFIG_PM_SLEEP
|
static int rockchip_saradc_suspend(struct device *dev)
|
{
|
struct iio_dev *indio_dev = dev_get_drvdata(dev);
|
struct rockchip_saradc *info = iio_priv(indio_dev);
|
|
/* Avoid reading saradc when suspending */
|
mutex_lock(&indio_dev->mlock);
|
|
clk_disable_unprepare(info->clk);
|
clk_disable_unprepare(info->pclk);
|
regulator_disable(info->vref);
|
|
info->suspended = true;
|
mutex_unlock(&indio_dev->mlock);
|
|
return 0;
|
}
|
|
static int rockchip_saradc_resume(struct device *dev)
|
{
|
struct iio_dev *indio_dev = dev_get_drvdata(dev);
|
struct rockchip_saradc *info = iio_priv(indio_dev);
|
int ret;
|
|
ret = regulator_enable(info->vref);
|
if (ret)
|
return ret;
|
|
ret = clk_prepare_enable(info->pclk);
|
if (ret)
|
return ret;
|
|
ret = clk_prepare_enable(info->clk);
|
if (ret)
|
clk_disable_unprepare(info->pclk);
|
|
info->suspended = false;
|
|
return ret;
|
}
|
#endif
|
|
static SIMPLE_DEV_PM_OPS(rockchip_saradc_pm_ops,
|
rockchip_saradc_suspend, rockchip_saradc_resume);
|
|
static struct platform_driver rockchip_saradc_driver = {
|
.probe = rockchip_saradc_probe,
|
.driver = {
|
.name = "rockchip-saradc",
|
.of_match_table = rockchip_saradc_match,
|
.pm = &rockchip_saradc_pm_ops,
|
},
|
};
|
|
module_platform_driver(rockchip_saradc_driver);
|
|
MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
|
MODULE_DESCRIPTION("Rockchip SARADC driver");
|
MODULE_LICENSE("GPL v2");
|
