/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_MICROCODE_AMD_H
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#define _ASM_X86_MICROCODE_AMD_H
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#include <asm/microcode.h>
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#define UCODE_MAGIC 0x00414d44
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#define UCODE_EQUIV_CPU_TABLE_TYPE 0x00000000
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#define UCODE_UCODE_TYPE 0x00000001
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#define SECTION_HDR_SIZE 8
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#define CONTAINER_HDR_SZ 12
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struct equiv_cpu_entry {
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u32 installed_cpu;
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u32 fixed_errata_mask;
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u32 fixed_errata_compare;
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u16 equiv_cpu;
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u16 res;
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} __attribute__((packed));
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struct microcode_header_amd {
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u32 data_code;
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u32 patch_id;
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u16 mc_patch_data_id;
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u8 mc_patch_data_len;
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u8 init_flag;
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u32 mc_patch_data_checksum;
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u32 nb_dev_id;
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u32 sb_dev_id;
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u16 processor_rev_id;
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u8 nb_rev_id;
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u8 sb_rev_id;
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u8 bios_api_rev;
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u8 reserved1[3];
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u32 match_reg[8];
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} __attribute__((packed));
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struct microcode_amd {
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struct microcode_header_amd hdr;
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unsigned int mpb[0];
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};
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#define PATCH_MAX_SIZE (3 * PAGE_SIZE)
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#ifdef CONFIG_MICROCODE_AMD
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extern void __init load_ucode_amd_bsp(unsigned int family);
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extern void load_ucode_amd_ap(unsigned int family);
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extern int __init save_microcode_in_initrd_amd(unsigned int family);
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void reload_ucode_amd(void);
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#else
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static inline void __init load_ucode_amd_bsp(unsigned int family) {}
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static inline void load_ucode_amd_ap(unsigned int family) {}
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static inline int __init
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save_microcode_in_initrd_amd(unsigned int family) { return -EINVAL; }
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static inline void reload_ucode_amd(void) {}
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#endif
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#endif /* _ASM_X86_MICROCODE_AMD_H */
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