1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
| /* SPDX-License-Identifier: GPL-2.0+ WITH GCC-exception-2.0
|
| Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
| 2004, 2005
| Free Software Foundation, Inc.
| */
|
| !! libgcc routines for the Renesas / SuperH SH CPUs.
| !! Contributed by Steve Chamberlain.
| !! sac@cygnus.com
|
| .balign 4
| .global __udivsi3
| .type __udivsi3, @function
| div8:
| div1 r5,r4
| div7:
| div1 r5,r4; div1 r5,r4; div1 r5,r4
| div1 r5,r4; div1 r5,r4; div1 r5,r4; rts; div1 r5,r4
|
| divx4:
| div1 r5,r4; rotcl r0
| div1 r5,r4; rotcl r0
| div1 r5,r4; rotcl r0
| rts; div1 r5,r4
|
| __udivsi3:
| sts.l pr,@-r15
| extu.w r5,r0
| cmp/eq r5,r0
| bf/s large_divisor
| div0u
| swap.w r4,r0
| shlr16 r4
| bsr div8
| shll16 r5
| bsr div7
| div1 r5,r4
| xtrct r4,r0
| xtrct r0,r4
| bsr div8
| swap.w r4,r4
| bsr div7
| div1 r5,r4
| lds.l @r15+,pr
| xtrct r4,r0
| swap.w r0,r0
| rotcl r0
| rts
| shlr16 r5
|
| large_divisor:
| mov #0,r0
| xtrct r4,r0
| xtrct r0,r4
| bsr divx4
| rotcl r0
| bsr divx4
| rotcl r0
| bsr divx4
| rotcl r0
| bsr divx4
| rotcl r0
| lds.l @r15+,pr
| rts
| rotcl r0
|
|
