/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* contains some Q40 related interrupt definitions
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*/
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#define Q40_IRQ_MAX (34)
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#define Q40_IRQ_SAMPLE (34)
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#define Q40_IRQ_KEYBOARD (32)
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#define Q40_IRQ_FRAME (33)
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/* masks for interrupt regiosters*/
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/* internal, IIRQ_REG */
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#define Q40_IRQ_KEYB_MASK (2)
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#define Q40_IRQ_SER_MASK (1<<2)
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#define Q40_IRQ_FRAME_MASK (1<<3)
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#define Q40_IRQ_EXT_MASK (1<<4) /* is a EIRQ */
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/* eirq, EIRQ_REG */
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#define Q40_IRQ3_MASK (1)
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#define Q40_IRQ4_MASK (1<<1)
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#define Q40_IRQ5_MASK (1<<2)
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#define Q40_IRQ6_MASK (1<<3)
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#define Q40_IRQ7_MASK (1<<4)
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#define Q40_IRQ10_MASK (1<<5)
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#define Q40_IRQ14_MASK (1<<6)
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#define Q40_IRQ15_MASK (1<<7)
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