/** @file
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Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
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Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef OGMA_REG_F_GMAC_4MT_H
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#define OGMA_REG_F_GMAC_4MT_H
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/**
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* GMAC register
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*/
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#define OGMA_GMAC_REG_ADDR_MCR (0x0000)
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#define OGMA_GMAC_REG_ADDR_MFFR (0x0004)
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#define OGMA_GMAC_REG_ADDR_MHTRH (0x0008)
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#define OGMA_GMAC_REG_ADDR_MHTRL (0x000c)
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#define OGMA_GMAC_REG_ADDR_GAR (0x0010)
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#define OGMA_GMAC_REG_ADDR_GDR (0x0014)
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#define OGMA_GMAC_REG_ADDR_FCR (0x0018)
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#define OGMA_GMAC_REG_ADDR_VTR (0x001c)
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#define OGMA_GMAC_REG_ADDR_RWFFR (0x0028)
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#define OGMA_GMAC_REG_ADDR_PMTR (0x002c)
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#define OGMA_GMAC_REG_ADDR_LPICSR (0x0030)
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#define OGMA_GMAC_REG_ADDR_LPITCR (0x0034)
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#define OGMA_GMAC_REG_ADDR_ISR (0x0038)
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#define OGMA_GMAC_REG_ADDR_IMR (0x003c)
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#define OGMA_GMAC_REG_ADDR_MAR0H (0x0040)
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#define OGMA_GMAC_REG_ADDR_MAR0L (0x0044)
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#define OGMA_GMAC_REG_ADDR_MAR1H (0x0048)
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#define OGMA_GMAC_REG_ADDR_MAR1L (0x004c)
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#define OGMA_GMAC_REG_ADDR_MAR2H (0x0050)
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#define OGMA_GMAC_REG_ADDR_MAR2L (0x0054)
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#define OGMA_GMAC_REG_ADDR_MAR3H (0x0058)
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#define OGMA_GMAC_REG_ADDR_MAR3L (0x005c)
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#define OGMA_GMAC_REG_ADDR_MAR4H (0x0060)
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#define OGMA_GMAC_REG_ADDR_MAR4L (0x0064)
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#define OGMA_GMAC_REG_ADDR_MAR5H (0x0068)
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#define OGMA_GMAC_REG_ADDR_MAR5L (0x006c)
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#define OGMA_GMAC_REG_ADDR_MAR6H (0x0070)
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#define OGMA_GMAC_REG_ADDR_MAR6L (0x0074)
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#define OGMA_GMAC_REG_ADDR_MAR7H (0x0078)
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#define OGMA_GMAC_REG_ADDR_MAR7L (0x007c)
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#define OGMA_GMAC_REG_ADDR_MAR8H (0x0080)
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#define OGMA_GMAC_REG_ADDR_MAR8L (0x0084)
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#define OGMA_GMAC_REG_ADDR_MAR9H (0x0088)
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#define OGMA_GMAC_REG_ADDR_MAR9L (0x008c)
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#define OGMA_GMAC_REG_ADDR_MAR10H (0x0090)
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#define OGMA_GMAC_REG_ADDR_MAR10L (0x0094)
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#define OGMA_GMAC_REG_ADDR_MAR11H (0x0098)
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#define OGMA_GMAC_REG_ADDR_MAR11L (0x009c)
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#define OGMA_GMAC_REG_ADDR_MAR12H (0x00a0)
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#define OGMA_GMAC_REG_ADDR_MAR12L (0x00a4)
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#define OGMA_GMAC_REG_ADDR_MAR13H (0x00a8)
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#define OGMA_GMAC_REG_ADDR_MAR13L (0x00ac)
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#define OGMA_GMAC_REG_ADDR_MAR14H (0x00b0)
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#define OGMA_GMAC_REG_ADDR_MAR14L (0x00b4)
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#define OGMA_GMAC_REG_ADDR_MAR15H (0x00b8)
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#define OGMA_GMAC_REG_ADDR_MAR15L (0x00bc)
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#define OGMA_GMAC_REG_ADDR_RSR (0x00d8)
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#define OGMA_GMAC_REG_ADDR_TSCR (0x0700)
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#define OGMA_GMAC_REG_ADDR_SSIR (0x0704)
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#define OGMA_GMAC_REG_ADDR_STSR (0x0708)
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#define OGMA_GMAC_REG_ADDR_STNR (0x070c)
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#define OGMA_GMAC_REG_ADDR_STSUR (0x0710)
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#define OGMA_GMAC_REG_ADDR_STNUR (0x0714)
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#define OGMA_GMAC_REG_ADDR_TSAR (0x0718)
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#define OGMA_GMAC_REG_ADDR_TTSR (0x071c)
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#define OGMA_GMAC_REG_ADDR_TTNR (0x0720)
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#define OGMA_GMAC_REG_ADDR_STHWSR (0x0724)
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#define OGMA_GMAC_REG_ADDR_TSR (0x0728)
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#define OGMA_GMAC_REG_ADDR_PPSCR (0x072c)
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#define OGMA_GMAC_REG_ADDR_ANTR (0x0730)
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#define OGMA_GMAC_REG_ADDR_ATSR (0x0734)
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#define OGMA_GMAC_REG_ADDR_MAR16H (0x0800)
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#define OGMA_GMAC_REG_ADDR_MAR16L (0x0804)
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#define OGMA_GMAC_REG_ADDR_MAR17H (0x0808)
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#define OGMA_GMAC_REG_ADDR_MAR17L (0x080c)
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#define OGMA_GMAC_REG_ADDR_MAR18H (0x0810)
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#define OGMA_GMAC_REG_ADDR_MAR18L (0x0814)
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#define OGMA_GMAC_REG_ADDR_MAR19H (0x0818)
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#define OGMA_GMAC_REG_ADDR_MAR19L (0x081c)
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#define OGMA_GMAC_REG_ADDR_MAR20H (0x0820)
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#define OGMA_GMAC_REG_ADDR_MAR20L (0x0824)
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#define OGMA_GMAC_REG_ADDR_MAR21H (0x0828)
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#define OGMA_GMAC_REG_ADDR_MAR21L (0x082c)
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#define OGMA_GMAC_REG_ADDR_MAR22H (0x0830)
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#define OGMA_GMAC_REG_ADDR_MAR22L (0x0834)
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#define OGMA_GMAC_REG_ADDR_MAR23H (0x0838)
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#define OGMA_GMAC_REG_ADDR_MAR23L (0x083c)
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#define OGMA_GMAC_REG_ADDR_MAR24H (0x0840)
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#define OGMA_GMAC_REG_ADDR_MAR24L (0x0844)
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#define OGMA_GMAC_REG_ADDR_MAR25H (0x0848)
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#define OGMA_GMAC_REG_ADDR_MAR25L (0x084c)
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#define OGMA_GMAC_REG_ADDR_MAR26H (0x0850)
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#define OGMA_GMAC_REG_ADDR_MAR26L (0x0854)
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#define OGMA_GMAC_REG_ADDR_MAR27H (0x0858)
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#define OGMA_GMAC_REG_ADDR_MAR27L (0x085c)
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#define OGMA_GMAC_REG_ADDR_MAR28H (0x0860)
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#define OGMA_GMAC_REG_ADDR_MAR28L (0x0864)
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#define OGMA_GMAC_REG_ADDR_MAR29H (0x0868)
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#define OGMA_GMAC_REG_ADDR_MAR29L (0x086c)
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#define OGMA_GMAC_REG_ADDR_MAR30H (0x0870)
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#define OGMA_GMAC_REG_ADDR_MAR30L (0x0874)
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#define OGMA_GMAC_REG_ADDR_MAR31H (0x0878)
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#define OGMA_GMAC_REG_ADDR_MAR31L (0x087c)
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/**
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* GMAC MAC Management Counters(Option) register
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*/
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#define OGMA_GMAC_REG_ADDR_MMC_CNTL (0x0100)
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#define OGMA_GMAC_REG_ADDR_MMC_INTR_RX (0x0104)
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#define OGMA_GMAC_REG_ADDR_MMC_INTR_TX (0x0108)
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#define OGMA_GMAC_REG_ADDR_MMC_INTR_MASK_RX (0x010c)
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#define OGMA_GMAC_REG_ADDR_MMC_INTR_MASK_TX (0x0110)
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#define OGMA_GMAC_REG_ADDR_TXOCTETCOUNT_GB (0x0114)
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#define OGMA_GMAC_REG_ADDR_TXFRAMECOUNT_GB (0x0118)
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#define OGMA_GMAC_REG_ADDR_TXBROADCASTFRAMES_G (0x011c)
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#define OGMA_GMAC_REG_ADDR_TXMULTICASTFRAMES_G (0x0120)
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#define OGMA_GMAC_REG_ADDR_TX64OCTETS_GB (0x0124)
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#define OGMA_GMAC_REG_ADDR_TX65TO127OCTETS_GB (0x0128)
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#define OGMA_GMAC_REG_ADDR_TX128TO255OCTETS_GB (0x012c)
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#define OGMA_GMAC_REG_ADDR_TX256TO511OCTETS_GB (0x0130)
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#define OGMA_GMAC_REG_ADDR_TX512TO1023OCTETS_GB (0x0134)
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#define OGMA_GMAC_REG_ADDR_TX1024TOMAXOCTETS_GB (0x0138)
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#define OGMA_GMAC_REG_ADDR_TXUNICASTFRAMES_GB (0x013c)
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#define OGMA_GMAC_REG_ADDR_TXMULTICASTFRAMES_GB (0x0140)
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#define OGMA_GMAC_REG_ADDR_TXBROADCASTFRAMES_GB (0x0144)
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#define OGMA_GMAC_REG_ADDR_TXUNDERFLOWERROR (0x0148)
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#define OGMA_GMAC_REG_ADDR_TXSINGLECOL_G (0x014c)
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#define OGMA_GMAC_REG_ADDR_TXMULTICOL_G (0x0150)
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#define OGMA_GMAC_REG_ADDR_TXDEFERRED (0x0154)
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#define OGMA_GMAC_REG_ADDR_TXLATECOL (0x0158)
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#define OGMA_GMAC_REG_ADDR_TXEXESSCOL (0x015c)
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#define OGMA_GMAC_REG_ADDR_TXCARRIERERRROR (0x0160)
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#define OGMA_GMAC_REG_ADDR_TXOCTETCOUNT_G (0x0164)
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#define OGMA_GMAC_REG_ADDR_TXFRAMECOUNT_G (0x0168)
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#define OGMA_GMAC_REG_ADDR_TXEXECESSDEF (0x016c)
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#define OGMA_GMAC_REG_ADDR_TXPAUSEFRAMES (0x0170)
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#define OGMA_GMAC_REG_ADDR_TXVLANFRAMES_G (0x0174)
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#define OGMA_GMAC_REG_ADDR_RXFRAMECOUNT_GB (0x0180)
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#define OGMA_GMAC_REG_ADDR_RXOCTETCOUNT_GB (0x0184)
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#define OGMA_GMAC_REG_ADDR_RXOCTETCOUNT_G (0x0188)
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#define OGMA_GMAC_REG_ADDR_RXBROADCASTFRAMES_G (0x018c)
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#define OGMA_GMAC_REG_ADDR_RXMULTICASTFRAMES_G (0x0190)
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#define OGMA_GMAC_REG_ADDR_RXCRCERROR (0x0194)
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#define OGMA_GMAC_REG_ADDR_RXALLIGNMENTERROR (0x0198)
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#define OGMA_GMAC_REG_ADDR_RXRUNTERROR (0x019c)
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#define OGMA_GMAC_REG_ADDR_RXJABBERERROR (0x01a0)
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#define OGMA_GMAC_REG_ADDR_RXUNDERSIZE_G (0x01a4)
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#define OGMA_GMAC_REG_ADDR_RXOVERSIZE_G (0x01a8)
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#define OGMA_GMAC_REG_ADDR_RX64OCTETS_GB (0x01ac)
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#define OGMA_GMAC_REG_ADDR_RX65TO127OCTETS_GB (0x01b0)
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#define OGMA_GMAC_REG_ADDR_RX128TO255OCTETS_GB (0x01b4)
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#define OGMA_GMAC_REG_ADDR_RX256TO511OCTETS_GB (0x01b8)
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#define OGMA_GMAC_REG_ADDR_RX512TO1023OCTETS_GB (0x01bc)
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#define OGMA_GMAC_REG_ADDR_RX1024TOMAXOCTETS_GB (0x01c0)
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#define OGMA_GMAC_REG_ADDR_RXUNICASTFRAMES_G (0x01c4)
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#define OGMA_GMAC_REG_ADDR_RXLENGTHERROR (0x01c8)
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#define OGMA_GMAC_REG_ADDR_RXOUTOFRANGETYPE (0x01cc)
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#define OGMA_GMAC_REG_ADDR_RXPAUSEFRAMES (0x01d0)
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#define OGMA_GMAC_REG_ADDR_RXFIFOOVERFLOW (0x01d4)
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#define OGMA_GMAC_REG_ADDR_RXVLANFRAMES_GB (0x01d8)
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#define OGMA_GMAC_REG_ADDR_RXWATCHDOGERROR (0x01dc)
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#define OGMA_GMAC_REG_ADDR_MMC_IPC_INTR_MASK_RX (0x0200)
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#define OGMA_GMAC_REG_ADDR_MMC_IPC_INTR_RX (0x0208)
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#define OGMA_GMAC_REG_ADDR_RXIPV4_GD_FRMS (0x0210)
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#define OGMA_GMAC_REG_ADDR_RXIPV4_HDRERR_FRMS (0x0214)
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#define OGMA_GMAC_REG_ADDR_RXIPV4_NOPAY_FRMS (0x0218)
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#define OGMA_GMAC_REG_ADDR_RXIPV4_FRAG_FRMS (0x021c)
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#define OGMA_GMAC_REG_ADDR_RXIPV4_UDSBL_FRMS (0x0220)
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#define OGMA_GMAC_REG_ADDR_RXIPV6_GD_FRMS (0x0224)
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#define OGMA_GMAC_REG_ADDR_RXIPV6_HDRERR_FRMS (0x0228)
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#define OGMA_GMAC_REG_ADDR_RXIPV6_NOPAY_FRMS (0x022c)
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#define OGMA_GMAC_REG_ADDR_RXUDP_GD_FRMS (0x0230)
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#define OGMA_GMAC_REG_ADDR_RXUDP_ERR_FRMS (0x0234)
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#define OGMA_GMAC_REG_ADDR_RXTCP_GD_FRMS (0x0238)
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#define OGMA_GMAC_REG_ADDR_RXTCP_ERR_FRMS (0x023c)
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#define OGMA_GMAC_REG_ADDR_RXICMP_GD_FRMS (0x0240)
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#define OGMA_GMAC_REG_ADDR_RXICMP_ERR_FRMS (0x0244)
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#define OGMA_GMAC_REG_ADDR_RXIPV4_GD_OCTETS (0x0250)
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#define OGMA_GMAC_REG_ADDR_RXIPV4_HDRERR_OCTETS (0x0254)
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#define OGMA_GMAC_REG_ADDR_RXIPV4_NOPAY_OCTETS (0x0258)
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#define OGMA_GMAC_REG_ADDR_RXIPV4_FRAG_OCTETS (0x025c)
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#define OGMA_GMAC_REG_ADDR_RXIPV4_UDSBL_OCTETS (0x0260)
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#define OGMA_GMAC_REG_ADDR_RXIPV6_GD_OCTETS (0x0264)
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#define OGMA_GMAC_REG_ADDR_RXIPV6_HDRERR_OCTETS (0x0268)
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#define OGMA_GMAC_REG_ADDR_RXIPV6_NOPAY_OCTETS (0x026c)
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#define OGMA_GMAC_REG_ADDR_RXUDP_GD_OCTETS (0x0270)
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#define OGMA_GMAC_REG_ADDR_RXUDP_ERR_OCTETS (0x0274)
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#define OGMA_GMAC_REG_ADDR_RXTCP_GD_OCTETS (0x0278)
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#define OGMA_GMAC_REG_ADDR_RXTCP_ERR_OCTETS (0x027c)
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#define OGMA_GMAC_REG_ADDR_RXICMP_GD_OCTETS (0x0280)
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#define OGMA_GMAC_REG_ADDR_RXICMP_ERR_OCTETS (0x0284)
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/**
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* GMAC DMA register
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*/
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#define OGMA_GMAC_REG_ADDR_BMR (0x1000)
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#define OGMA_GMAC_REG_ADDR_TPDR (0x1004)
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#define OGMA_GMAC_REG_ADDR_RPDR (0x1008)
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#define OGMA_GMAC_REG_ADDR_RDLAR (0x100c)
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#define OGMA_GMAC_REG_ADDR_TDLAR (0x1010)
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#define OGMA_GMAC_REG_ADDR_SR (0x1014)
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#define OGMA_GMAC_REG_ADDR_OMR (0x1018)
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#define OGMA_GMAC_REG_ADDR_IER (0x101c)
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#define OGMA_GMAC_REG_ADDR_MFOCR (0x1020)
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#define OGMA_GMAC_REG_ADDR_RIWTR (0x1024)
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#define OGMA_GMAC_REG_ADDR_AHBSR (0x102c)
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#define OGMA_GMAC_REG_ADDR_CHTDR (0x1048)
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#define OGMA_GMAC_REG_ADDR_CHRDR (0x104c)
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#define OGMA_GMAC_REG_ADDR_CHTBAR (0x1050)
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#define OGMA_GMAC_REG_ADDR_CHRBAR (0x1054)
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#endif /* OGMA_REG_F_GMAC_4MT_H */
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