/*******************************************************************************
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Copyright (C) 2016 Marvell International Ltd.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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*******************************************************************************/
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#include "MvSpiOrionDxe.h"
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SPI_MASTER *mSpiMasterInstance;
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STATIC
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EFI_STATUS
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SpiSetBaudRate (
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IN SPI_DEVICE *Slave,
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IN UINT32 CpuClock,
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IN UINT32 MaxFreq
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)
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{
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UINT32 Spr, BestSpr, Sppr, BestSppr, ClockDivider, Match, Reg, MinBaudDiff;
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UINTN SpiRegBase = Slave->HostRegisterBaseAddress;
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MinBaudDiff = 0xFFFFFFFF;
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BestSppr = 0;
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//Spr is in range 1-15 and Sppr in range 0-8
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for (Spr = 1; Spr <= 15; Spr++) {
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for (Sppr = 0; Sppr <= 7; Sppr++) {
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ClockDivider = Spr * (1 << Sppr);
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if ((CpuClock / ClockDivider) > MaxFreq) {
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continue;
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}
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if ((CpuClock / ClockDivider) == MaxFreq) {
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BestSpr = Spr;
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BestSppr = Sppr;
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Match = 1;
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break;
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}
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if ((MaxFreq - (CpuClock / ClockDivider)) < MinBaudDiff) {
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MinBaudDiff = (MaxFreq - (CpuClock / ClockDivider));
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BestSpr = Spr;
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BestSppr = Sppr;
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}
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}
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if (Match == 1) {
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break;
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}
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}
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if (BestSpr == 0) {
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return (EFI_INVALID_PARAMETER);
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}
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Reg = MmioRead32 (SpiRegBase + SPI_CONF_REG);
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Reg &= ~(SPI_SPR_MASK | SPI_SPPR_0_MASK | SPI_SPPR_HI_MASK);
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Reg |= (BestSpr << SPI_SPR_OFFSET) |
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((BestSppr & 0x1) << SPI_SPPR_0_OFFSET) |
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((BestSppr >> 1) << SPI_SPPR_HI_OFFSET);
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MmioWrite32 (SpiRegBase + SPI_CONF_REG, Reg);
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return EFI_SUCCESS;
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}
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STATIC
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VOID
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SpiSetCs (
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IN SPI_DEVICE *Slave
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)
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{
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UINT32 Reg;
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UINTN SpiRegBase = Slave->HostRegisterBaseAddress;
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Reg = MmioRead32 (SpiRegBase + SPI_CTRL_REG);
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Reg &= ~SPI_CS_NUM_MASK;
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Reg |= (Slave->Cs << SPI_CS_NUM_OFFSET);
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MmioWrite32 (SpiRegBase + SPI_CTRL_REG, Reg);
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}
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STATIC
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VOID
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SpiActivateCs (
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IN SPI_DEVICE *Slave
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)
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{
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UINT32 Reg;
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UINTN SpiRegBase = Slave->HostRegisterBaseAddress;
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SpiSetCs(Slave);
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Reg = MmioRead32 (SpiRegBase + SPI_CTRL_REG);
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Reg |= SPI_CS_EN_MASK;
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MmioWrite32(SpiRegBase + SPI_CTRL_REG, Reg);
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}
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STATIC
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VOID
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SpiDeactivateCs (
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IN SPI_DEVICE *Slave
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)
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{
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UINT32 Reg;
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UINTN SpiRegBase = Slave->HostRegisterBaseAddress;
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Reg = MmioRead32 (SpiRegBase + SPI_CTRL_REG);
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Reg &= ~SPI_CS_EN_MASK;
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MmioWrite32(SpiRegBase + SPI_CTRL_REG, Reg);
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}
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STATIC
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VOID
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SpiSetupTransfer (
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IN MARVELL_SPI_MASTER_PROTOCOL *This,
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IN SPI_DEVICE *Slave
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)
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{
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SPI_MASTER *SpiMaster;
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UINT32 Reg, CoreClock, SpiMaxFreq;
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UINTN SpiRegBase;
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SpiMaster = SPI_MASTER_FROM_SPI_MASTER_PROTOCOL (This);
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// Initialize values from PCDs
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SpiRegBase = Slave->HostRegisterBaseAddress;
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CoreClock = Slave->CoreClock;
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SpiMaxFreq = Slave->MaxFreq;
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EfiAcquireLock (&SpiMaster->Lock);
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Reg = MmioRead32 (SpiRegBase + SPI_CONF_REG);
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Reg |= SPI_BYTE_LENGTH;
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MmioWrite32 (SpiRegBase + SPI_CONF_REG, Reg);
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SpiSetCs(Slave);
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SpiSetBaudRate (Slave, CoreClock, SpiMaxFreq);
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Reg = MmioRead32 (SpiRegBase + SPI_CONF_REG);
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Reg &= ~(SPI_CPOL_MASK | SPI_CPHA_MASK | SPI_TXLSBF_MASK | SPI_RXLSBF_MASK);
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switch (Slave->Mode) {
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case SPI_MODE0:
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break;
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case SPI_MODE1:
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Reg |= SPI_CPHA_MASK;
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break;
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case SPI_MODE2:
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Reg |= SPI_CPOL_MASK;
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break;
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case SPI_MODE3:
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Reg |= SPI_CPOL_MASK;
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Reg |= SPI_CPHA_MASK;
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break;
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}
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MmioWrite32 (SpiRegBase + SPI_CONF_REG, Reg);
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EfiReleaseLock (&SpiMaster->Lock);
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}
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EFI_STATUS
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EFIAPI
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MvSpiTransfer (
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IN MARVELL_SPI_MASTER_PROTOCOL *This,
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IN SPI_DEVICE *Slave,
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IN UINTN DataByteCount,
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IN VOID *DataOut,
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IN VOID *DataIn,
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IN UINTN Flag
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)
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{
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SPI_MASTER *SpiMaster;
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UINT64 Length;
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UINT32 Iterator, Reg;
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UINT8 *DataOutPtr = (UINT8 *)DataOut;
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UINT8 *DataInPtr = (UINT8 *)DataIn;
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UINT8 DataToSend = 0;
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UINTN SpiRegBase;
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SpiMaster = SPI_MASTER_FROM_SPI_MASTER_PROTOCOL (This);
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SpiRegBase = Slave->HostRegisterBaseAddress;
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Length = 8 * DataByteCount;
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if (!EfiAtRuntime ()) {
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EfiAcquireLock (&SpiMaster->Lock);
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}
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if (Flag & SPI_TRANSFER_BEGIN) {
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SpiActivateCs (Slave);
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}
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// Set 8-bit mode
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Reg = MmioRead32 (SpiRegBase + SPI_CONF_REG);
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Reg &= ~SPI_BYTE_LENGTH;
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MmioWrite32 (SpiRegBase + SPI_CONF_REG, Reg);
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while (Length > 0) {
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if (DataOut != NULL) {
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DataToSend = *DataOutPtr & 0xFF;
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}
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// Transmit Data
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MmioWrite32 (SpiRegBase + SPI_INT_CAUSE_REG, 0x0);
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MmioWrite32 (SpiRegBase + SPI_DATA_OUT_REG, DataToSend);
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// Wait for memory ready
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for (Iterator = 0; Iterator < SPI_TIMEOUT; Iterator++) {
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if (MmioRead32 (SpiRegBase + SPI_INT_CAUSE_REG)) {
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if (DataInPtr != NULL) {
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*DataInPtr = MmioRead32 (SpiRegBase + SPI_DATA_IN_REG);
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DataInPtr++;
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}
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if (DataOutPtr != NULL) {
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DataOutPtr++;
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}
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Length -= 8;
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break;
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}
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}
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if (Iterator >= SPI_TIMEOUT) {
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DEBUG ((DEBUG_ERROR, "%a: Timeout\n", __FUNCTION__));
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return EFI_TIMEOUT;
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}
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}
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if (Flag & SPI_TRANSFER_END) {
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SpiDeactivateCs (Slave);
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}
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if (!EfiAtRuntime ()) {
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EfiReleaseLock (&SpiMaster->Lock);
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}
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return EFI_SUCCESS;
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}
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EFI_STATUS
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EFIAPI
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MvSpiReadWrite (
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IN MARVELL_SPI_MASTER_PROTOCOL *This,
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IN SPI_DEVICE *Slave,
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IN UINT8 *Cmd,
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IN UINTN CmdSize,
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IN UINT8 *DataOut,
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OUT UINT8 *DataIn,
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IN UINTN DataSize
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)
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{
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EFI_STATUS Status;
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Status = MvSpiTransfer (This, Slave, CmdSize, Cmd, NULL, SPI_TRANSFER_BEGIN);
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if (EFI_ERROR (Status)) {
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Print (L"Spi Transfer Error\n");
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return EFI_DEVICE_ERROR;
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}
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Status = MvSpiTransfer (This, Slave, DataSize, DataOut, DataIn, SPI_TRANSFER_END);
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if (EFI_ERROR (Status)) {
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Print (L"Spi Transfer Error\n");
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return EFI_DEVICE_ERROR;
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}
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return EFI_SUCCESS;
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}
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EFI_STATUS
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EFIAPI
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MvSpiInit (
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IN MARVELL_SPI_MASTER_PROTOCOL * This
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)
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{
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return EFI_SUCCESS;
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}
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SPI_DEVICE *
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EFIAPI
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MvSpiSetupSlave (
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IN MARVELL_SPI_MASTER_PROTOCOL *This,
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IN SPI_DEVICE *Slave,
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IN UINTN Cs,
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IN SPI_MODE Mode
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)
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{
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if (!Slave) {
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Slave = AllocateZeroPool (sizeof(SPI_DEVICE));
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if (Slave == NULL) {
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DEBUG((DEBUG_ERROR, "Cannot allocate memory\n"));
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return NULL;
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}
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Slave->Cs = Cs;
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Slave->Mode = Mode;
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}
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Slave->HostRegisterBaseAddress = PcdGet32 (PcdSpiRegBase);
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Slave->CoreClock = PcdGet32 (PcdSpiClockFrequency);
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Slave->MaxFreq = PcdGet32 (PcdSpiMaxFrequency);
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SpiSetupTransfer (This, Slave);
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return Slave;
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}
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EFI_STATUS
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EFIAPI
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MvSpiFreeSlave (
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IN SPI_DEVICE *Slave
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)
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{
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FreePool (Slave);
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return EFI_SUCCESS;
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}
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EFI_STATUS
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EFIAPI
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MvSpiConfigRuntime (
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IN SPI_DEVICE *Slave
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)
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{
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EFI_STATUS Status;
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UINTN AlignedAddress;
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//
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// Host register base may be not aligned to the page size,
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// which is not accepted when setting memory space attributes.
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// Add one aligned page of memory space which covers the host
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// controller registers.
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//
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AlignedAddress = Slave->HostRegisterBaseAddress & ~(SIZE_4KB - 1);
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Status = gDS->AddMemorySpace (EfiGcdMemoryTypeMemoryMappedIo,
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AlignedAddress,
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SIZE_4KB,
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EFI_MEMORY_UC | EFI_MEMORY_RUNTIME);
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if (EFI_ERROR (Status)) {
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DEBUG ((DEBUG_ERROR, "%a: Failed to add memory space\n", __FUNCTION__));
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return Status;
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}
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Status = gDS->SetMemorySpaceAttributes (AlignedAddress,
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SIZE_4KB,
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EFI_MEMORY_UC | EFI_MEMORY_RUNTIME);
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if (EFI_ERROR (Status)) {
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DEBUG ((DEBUG_ERROR, "%a: Failed to set memory attributes\n", __FUNCTION__));
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gDS->RemoveMemorySpace (AlignedAddress, SIZE_4KB);
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return Status;
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}
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return EFI_SUCCESS;
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}
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STATIC
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EFI_STATUS
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SpiMasterInitProtocol (
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IN MARVELL_SPI_MASTER_PROTOCOL *SpiMasterProtocol
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)
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{
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SpiMasterProtocol->Init = MvSpiInit;
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SpiMasterProtocol->SetupDevice = MvSpiSetupSlave;
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SpiMasterProtocol->FreeDevice = MvSpiFreeSlave;
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SpiMasterProtocol->Transfer = MvSpiTransfer;
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SpiMasterProtocol->ReadWrite = MvSpiReadWrite;
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SpiMasterProtocol->ConfigRuntime = MvSpiConfigRuntime;
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return EFI_SUCCESS;
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}
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EFI_STATUS
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EFIAPI
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MvSpiOrionEntryPoint (
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IN EFI_HANDLE ImageHandle,
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IN EFI_SYSTEM_TABLE *SystemTable
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)
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{
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EFI_STATUS Status;
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mSpiMasterInstance = AllocateRuntimeZeroPool (sizeof (SPI_MASTER));
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if (mSpiMasterInstance == NULL) {
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return EFI_OUT_OF_RESOURCES;
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}
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EfiInitializeLock (&mSpiMasterInstance->Lock, TPL_NOTIFY);
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SpiMasterInitProtocol (&mSpiMasterInstance->SpiMasterProtocol);
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mSpiMasterInstance->Signature = SPI_MASTER_SIGNATURE;
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Status = gBS->InstallMultipleProtocolInterfaces (
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&(mSpiMasterInstance->Handle),
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&gMarvellSpiMasterProtocolGuid,
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&(mSpiMasterInstance->SpiMasterProtocol),
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NULL
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);
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if (EFI_ERROR (Status)) {
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FreePool (mSpiMasterInstance);
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return EFI_DEVICE_ERROR;
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}
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return EFI_SUCCESS;
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}
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