/** @file
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This file is PeiPchPolicy library.
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "PeiPchPolicyLibrary.h"
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/**
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mDevIntConfig[] table contains data on INTx and IRQ for each device.
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IRQ value for devices which use ITSS INTx->PIRQx mapping need to be set in a way
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that for each multifunctional Dxx:Fy same interrupt pins must map to the same IRQ.
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Those IRQ values will be used to update ITSS.PIRx register.
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In APIC relationship between PIRQs and IRQs is:
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PIRQA -> IRQ16
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PIRQB -> IRQ17
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PIRQC -> IRQ18
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PIRQD -> IRQ19
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PIRQE -> IRQ20
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PIRQF -> IRQ21
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PIRQG -> IRQ22
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PIRQH -> IRQ23
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Devices which use INTx->PIRQy mapping are: cAVS(in PCI mode), SMBus, GbE, TraceHub, PCIe,
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SATA, HECI, IDE-R, KT Redirection, xHCI, Thermal Subsystem, Camera IO Host Controller
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PCI Express Root Ports mapping should be programmed only with values as in below table (D27/28/29)
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otherwise _PRT methods in ACPI for RootPorts would require additional patching as
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PCIe Endpoint Device Interrupt is further subjected to INTx to PIRQy Mapping
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Configured IRQ values are not used if an OS chooses to be in PIC instead of APIC mode
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**/
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GLOBAL_REMOVE_IF_UNREFERENCED PCH_DEVICE_INTERRUPT_CONFIG mDevIntConfig[] = {
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// {31, 0, PchNoInt, 0}, // LPC/eSPI Interface, doesn't use interrupts
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// {31, 1, PchNoInt, 0}, // P2SB, doesn't use interrupts
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// {31, 2, PchNoInt, 0}, // PMC , doesn't use interrupts
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{31, 3, PchIntA, 16}, // cAVS(Audio, Voice, Speach), INTA is default, programmed in PciCfgSpace 3Dh
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{31, 4, PchIntA, 16}, // SMBus Controller, no default value, programmed in PciCfgSpace 3Dh
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// {31, 5, PchNoInt, 0}, // SPI , doesn't use interrupts
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{31, 6, PchIntA, 16}, // GbE Controller, INTA is default, programmed in PciCfgSpace 3Dh
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{31, 7, PchIntA, 16}, // TraceHub, INTA is default, RO register
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{30, 0, PchIntA, 20}, // SerialIo: UART #0, INTA is default, programmed in PCR[SERIALIO] + PCICFGCTRL[7]
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{30, 1, PchIntB, 21}, // SerialIo: UART #1, INTA is default, programmed in PCR[SERIALIO] + PCICFGCTRL[8]
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{30, 2, PchIntC, 22}, // SerialIo: SPI #0, INTA is default, programmed in PCR[SERIALIO] + PCICFGCTRL[10]
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{30, 3, PchIntD, 23}, // SerialIo: SPI #1, INTA is default, programmed in PCR[SERIALIO] + PCICFGCTRL[11]
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{30, 4, PchIntB, 21}, // SCS: eMMC (SKL PCH-LP Only)
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{30, 5, PchIntC, 22}, // SCS: SDIO (SKL PCH-LP Only)
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{30, 6, PchIntD, 23}, // SCS: SDCard (SKL PCH-LP Only)
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{29, 0, PchIntA, 16}, // PCI Express Port 9, INT is default, programmed in PciCfgSpace + FCh
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{29, 1, PchIntB, 17}, // PCI Express Port 10, INT is default, programmed in PciCfgSpace + FCh
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{29, 2, PchIntC, 18}, // PCI Express Port 11, INT is default, programmed in PciCfgSpace + FCh
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{29, 3, PchIntD, 19}, // PCI Express Port 12, INT is default, programmed in PciCfgSpace + FCh
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{29, 4, PchIntA, 16}, // PCI Express Port 13 (SKL PCH-H Only), INT is default, programmed in PciCfgSpace + FCh
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{29, 5, PchIntB, 17}, // PCI Express Port 14 (SKL PCH-H Only), INT is default, programmed in PciCfgSpace + FCh
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{29, 6, PchIntC, 18}, // PCI Express Port 15 (SKL PCH-H Only), INT is default, programmed in PciCfgSpace + FCh
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{29, 7, PchIntD, 19}, // PCI Express Port 16 (SKL PCH-H Only), INT is default, programmed in PciCfgSpace + FCh
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{28, 0, PchIntA, 16}, // PCI Express Port 1, INT is default, programmed in PciCfgSpace + FCh
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{28, 1, PchIntB, 17}, // PCI Express Port 2, INT is default, programmed in PciCfgSpace + FCh
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{28, 2, PchIntC, 18}, // PCI Express Port 3, INT is default, programmed in PciCfgSpace + FCh
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{28, 3, PchIntD, 19}, // PCI Express Port 4, INT is default, programmed in PciCfgSpace + FCh
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{28, 4, PchIntA, 16}, // PCI Express Port 5, INT is default, programmed in PciCfgSpace + FCh
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{28, 5, PchIntB, 17}, // PCI Express Port 6, INT is default, programmed in PciCfgSpace + FCh
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{28, 6, PchIntC, 18}, // PCI Express Port 7, INT is default, programmed in PciCfgSpace + FCh
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{28, 7, PchIntD, 19}, // PCI Express Port 8, INT is default, programmed in PciCfgSpace + FCh
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{27, 0, PchIntA, 16}, // PCI Express Port 17 (PCH-H Only), INT is default, programmed in PciCfgSpace + FCh
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{27, 1, PchIntB, 17}, // PCI Express Port 18 (PCH-H Only), INT is default, programmed in PciCfgSpace + FCh
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{27, 2, PchIntC, 18}, // PCI Express Port 19 (PCH-H Only), INT is default, programmed in PciCfgSpace + FCh
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{27, 3, PchIntD, 19}, // PCI Express Port 20 (PCH-H Only), INT is default, programmed in PciCfgSpace + FCh
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{27, 4, PchIntA, 16}, // PCI Express Port 21 (KBL PCH-H Only), INT is default, programmed in PciCfgSpace + FCh
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{27, 5, PchIntB, 17}, // PCI Express Port 22 (KBL PCH-H Only), INT is default, programmed in PciCfgSpace + FCh
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{27, 6, PchIntC, 18}, // PCI Express Port 23 (KBL PCH-H Only), INT is default, programmed in PciCfgSpace + FCh
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{27, 7, PchIntD, 19}, // PCI Express Port 24 (KBL PCH-H Only), INT is default, programmed in PciCfgSpace + FCh
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{25, 0, PchIntA, 32}, // SerialIo UART Controller #2, INTA is default, programmed in PCR[SERIALIO] + PCICFGCTRL[9]
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// {24, 0, 0, 0}, // Reserved (used by RST PCIe Storage Cycle Router)
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{23, 0, PchIntA, 16}, // SATA Controller, INTA is default, programmed in PciCfgSpace + 3Dh
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{22, 0, PchIntA, 16}, // CSME: HECI #1
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{22, 1, PchIntB, 17}, // CSME: HECI #2
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{22, 2, PchIntC, 18}, // CSME: IDE-Redirection (IDE-R)
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{22, 3, PchIntD, 19}, // CSME: Keyboard and Text (KT) Redirection
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{22, 4, PchIntA, 16}, // CSME: HECI #3
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// {22, 7, PchNoInt, 0}, // CSME: WLAN
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{21, 0, PchIntA, 16}, // SerialIo I2C Controller #0, INTA is default, programmed in PCR[SERIALIO] + PCICFGCTRL[1]
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{21, 1, PchIntB, 17}, // SerialIo I2C Controller #1, INTA is default, programmed in PCR[SERIALIO] + PCICFGCTRL[2]
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{21, 2, PchIntC, 18}, // SerialIo I2C Controller #2, INTA is default, programmed in PCR[SERIALIO] + PCICFGCTRL[3]
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{21, 3, PchIntD, 19}, // SerialIo I2C Controller #3, INTA is default, programmed in PCR[SERIALIO] + PCICFGCTRL[4]
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{20, 0, PchIntA, 16}, // USB 3.0 xHCI Controller, no default value, programmed in PciCfgSpace 3Dh
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{20, 1, PchIntB, 17}, // USB Device Controller (OTG)
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{20, 2, PchIntC, 18}, // Thermal Subsystem
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{20, 3, PchIntA, 16}, // Camera IO Host Controller
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// {20, 4, 0, 0}, // TraceHub Phantom (ACPI) Function
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{19, 0, PchIntA, 20}, // Integrated Sensor Hub
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// {18, 0, PchNoInt, 0}, // CSME: KVMcc, doesn't use interrupts
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// {18, 1, PchNoInt, 0}, // CSME: Clink, doesn't use interrupts
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// {18, 2, PchNoInt, 0}, // CSME: PMT, doesn't use interrupts
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// {18, 3, 0, 0}, // CSME: CSE UMA
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// {18, 4, 0, 0} // CSME: fTPM DMA
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};
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//
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// mLpOnlyDevIntConfig[] table contains data on INTx and IRQ for devices that exist on SPT-LP but not on SPT-H.
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//
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GLOBAL_REMOVE_IF_UNREFERENCED PCH_DEVICE_INTERRUPT_CONFIG mLpOnlyDevIntConfig[] = {
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{25, 1, PchIntB, 33}, // SerialIo I2C Controller #5, INTA is default, programmed in PCR[SERIALIO] + PCICFGCTRL[6]
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{25, 2, PchIntC, 34} // SerialIo I2C Controller #4, INTA is default, programmed in PCR[SERIALIO] + PCICFGCTRL[5]
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};
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/**
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mPxRcConfig[] table contains data for 8259 routing (how PIRQx is mapped to IRQy).
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This information is used by systems which choose to use legacy PIC
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interrupt controller. Only IRQ3-7,9-12,14,15 are valid. Values from this table
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will be programmed into ITSS.PxRC registers.
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**/
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GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mPxRcConfig[] = {
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11, // PARC: PIRQA -> IRQ11
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10, // PBRC: PIRQB -> IRQ10
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11, // PCRC: PIRQC -> IRQ11
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11, // PDRC: PIRQD -> IRQ11
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11, // PERC: PIRQE -> IRQ11
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11, // PFRC: PIRQF -> IRQ11
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11, // PGRC: PIRQG -> IRQ11
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11 // PHRC: PIRQH -> IRQ11
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};
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/**
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Load Config block default
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@param[in] ConfigBlockPointer Pointer to config block
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**/
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VOID
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LoadPchGeneralConfigDefault (
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IN VOID *ConfigBlockPointer
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)
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{
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PCH_GENERAL_CONFIG *PchGeneralConfig;
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PchGeneralConfig = ConfigBlockPointer;
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DEBUG ((DEBUG_INFO, "PchGeneralConfig->Header.GuidHob.Name = %g\n", &PchGeneralConfig->Header.GuidHob.Name));
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DEBUG ((DEBUG_INFO, "PchGeneralConfig->Header.GuidHob.Header.HobLength = 0x%x\n", PchGeneralConfig->Header.GuidHob.Header.HobLength));
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/********************************
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PCH general configuration
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********************************/
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//
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// Default SVID SDID configuration
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//
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PchGeneralConfig->SubSystemVendorId = V_PCH_INTEL_VENDOR_ID;
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PchGeneralConfig->SubSystemId = V_PCH_DEFAULT_SID;
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}
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/**
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Load Config block default
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@param[in] ConfigBlockPointer Pointer to config block
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**/
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VOID
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LoadPcieRpConfigDefault (
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IN VOID *ConfigBlockPointer
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)
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{
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UINTN PortIndex;
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PCH_SERIES PchSeries;
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PCH_PCIE_CONFIG *PcieRpConfig;
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PcieRpConfig = ConfigBlockPointer;
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PchSeries = GetPchSeries ();
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DEBUG ((DEBUG_INFO, "PcieRpConfig->Header.GuidHob.Name = %g\n", &PcieRpConfig->Header.GuidHob.Name));
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DEBUG ((DEBUG_INFO, "PcieRpConfig->Header.GuidHob.Header.HobLength = 0x%x\n", PcieRpConfig->Header.GuidHob.Header.HobLength));
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/********************************
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PCI Express related settings
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********************************/
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PcieRpConfig->RpFunctionSwap = TRUE;
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for (PortIndex = 0; PortIndex < GetPchMaxPciePortNum (); PortIndex++) {
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PcieRpConfig->RootPort[PortIndex].Aspm = PchPcieAspmAutoConfig;
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PcieRpConfig->RootPort[PortIndex].PmSci = TRUE;
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PcieRpConfig->RootPort[PortIndex].AcsEnabled = TRUE;
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PcieRpConfig->RootPort[PortIndex].MaxPayload = PchPcieMaxPayload256;
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PcieRpConfig->RootPort[PortIndex].EnableHotplugSmi = TRUE;
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PcieRpConfig->RootPort[PortIndex].PhysicalSlotNumber = (UINT8) PortIndex;
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PcieRpConfig->RootPort[PortIndex].L1Substates = PchPcieL1SubstatesL1_1_2;
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PcieRpConfig->RootPort[PortIndex].EnableCpm = TRUE;
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//
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// PCIe LTR Configuration.
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//
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PcieRpConfig->RootPort[PortIndex].LtrEnable = TRUE;
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if (PchSeries == PchLp) {
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PcieRpConfig->RootPort[PortIndex].LtrMaxSnoopLatency = 0x1003;
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PcieRpConfig->RootPort[PortIndex].LtrMaxNoSnoopLatency = 0x1003;
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}
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if (PchSeries == PchH) {
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PcieRpConfig->RootPort[PortIndex].LtrMaxSnoopLatency = 0x0846;
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PcieRpConfig->RootPort[PortIndex].LtrMaxNoSnoopLatency = 0x0846;
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}
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PcieRpConfig->RootPort[PortIndex].SnoopLatencyOverrideMode = 2;
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PcieRpConfig->RootPort[PortIndex].SnoopLatencyOverrideMultiplier = 2;
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PcieRpConfig->RootPort[PortIndex].SnoopLatencyOverrideValue = 60;
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PcieRpConfig->RootPort[PortIndex].NonSnoopLatencyOverrideMode = 2;
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PcieRpConfig->RootPort[PortIndex].NonSnoopLatencyOverrideMultiplier = 2;
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PcieRpConfig->RootPort[PortIndex].NonSnoopLatencyOverrideValue = 60;
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PcieRpConfig->RootPort[PortIndex].Uptp = 5;
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PcieRpConfig->RootPort[PortIndex].Dptp = 7;
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PcieRpConfig->EqPh3LaneParam[PortIndex].Cm = 6;
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PcieRpConfig->EqPh3LaneParam[PortIndex].Cp = 2;
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}
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PcieRpConfig->SwEqCoeffList[0].Cm = 6;
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PcieRpConfig->SwEqCoeffList[0].Cp = 2;
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PcieRpConfig->SwEqCoeffList[1].Cm = 4;
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PcieRpConfig->SwEqCoeffList[1].Cp = 2;
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PcieRpConfig->SwEqCoeffList[2].Cm = 8;
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PcieRpConfig->SwEqCoeffList[2].Cp = 2;
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PcieRpConfig->SwEqCoeffList[3].Cm = 2;
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PcieRpConfig->SwEqCoeffList[3].Cp = 2;
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PcieRpConfig->SwEqCoeffList[4].Cm = 10;
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PcieRpConfig->SwEqCoeffList[4].Cp = 2;
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}
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/**
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Load Config block default
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@param[in] ConfigBlockPointer Pointer to config block
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**/
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VOID
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LoadSataConfigDefault (
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IN VOID *ConfigBlockPointer
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)
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{
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UINTN PortIndex;
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UINTN Index;
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PCH_SATA_CONFIG *SataConfig;
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SataConfig = ConfigBlockPointer;
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DEBUG ((DEBUG_INFO, "SataConfig->Header.GuidHob.Name = %g\n", &SataConfig->Header.GuidHob.Name));
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DEBUG ((DEBUG_INFO, "SataConfig->Header.GuidHob.Header.HobLength = 0x%x\n", SataConfig->Header.GuidHob.Header.HobLength));
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/********************************
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SATA related settings
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********************************/
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SataConfig->Enable = TRUE;
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SataConfig->SalpSupport = TRUE;
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SataConfig->SataMode = PchSataModeAhci;
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for (PortIndex = 0; PortIndex < GetPchMaxSataPortNum (); PortIndex++) {
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SataConfig->PortSettings[PortIndex].Enable = TRUE;
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SataConfig->PortSettings[PortIndex].DmVal = 15;
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SataConfig->PortSettings[PortIndex].DitoVal = 625;
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}
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SataConfig->Rst.Raid0 = TRUE;
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SataConfig->Rst.Raid1 = TRUE;
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SataConfig->Rst.Raid10 = TRUE;
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SataConfig->Rst.Raid5 = TRUE;
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SataConfig->Rst.Irrt = TRUE;
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SataConfig->Rst.OromUiBanner = TRUE;
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SataConfig->Rst.OromUiDelay = PchSataOromDelay2sec;
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SataConfig->Rst.HddUnlock = TRUE;
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SataConfig->Rst.LedLocate = TRUE;
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SataConfig->Rst.IrrtOnly = TRUE;
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SataConfig->Rst.SmartStorage = TRUE;
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SataConfig->Rst.OptaneMemory = TRUE;
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for (Index = 0; Index < PCH_MAX_RST_PCIE_STORAGE_CR; Index++) {
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SataConfig->RstPcieStorageRemap[Index].DeviceResetDelay = 100;
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}
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SataConfig->PwrOptEnable = TRUE;
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}
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/**
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Load Config block default
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@param[in] ConfigBlockPointer Pointer to config block
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**/
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VOID
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LoadIoApicConfigDefault (
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IN VOID *ConfigBlockPointer
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)
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{
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PCH_IOAPIC_CONFIG *IoApicConfig;
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IoApicConfig = ConfigBlockPointer;
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DEBUG ((DEBUG_INFO, "IoApicConfig->Header.GuidHob.Name = %g\n", &IoApicConfig->Header.GuidHob.Name));
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DEBUG ((DEBUG_INFO, "IoApicConfig->Header.GuidHob.Header.HobLength = 0x%x\n", IoApicConfig->Header.GuidHob.Header.HobLength));
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/********************************
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Io Apic configuration
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********************************/
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IoApicConfig->IoApicId = 0x02;
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IoApicConfig->IoApicEntry24_119 = TRUE;
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}
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/**
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Load Config block default
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@param[in] ConfigBlockPointer Pointer to config block
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**/
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VOID
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LoadCio2ConfigDefault (
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IN VOID *ConfigBlockPointer
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)
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{
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PCH_CIO2_CONFIG *Cio2Config;
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Cio2Config = ConfigBlockPointer;
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DEBUG ((DEBUG_INFO, "Cio2Config->Header.GuidHob.Name = %g\n", &Cio2Config->Header.GuidHob.Name));
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DEBUG ((DEBUG_INFO, "Cio2Config->Header.GuidHob.Header.HobLength = 0x%x\n", Cio2Config->Header.GuidHob.Header.HobLength));
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/********************************
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Initialize CIO2 Config and FLS config
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********************************/
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Cio2Config->DeviceEnable = TRUE;
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Cio2Config->PortATrimEnable = TRUE;
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Cio2Config->PortBTrimEnable = TRUE;
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Cio2Config->PortCTrimEnable = TRUE;
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Cio2Config->PortDTrimEnable = TRUE;
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Cio2Config->PortACtleEnable = TRUE;
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Cio2Config->PortBCtleEnable = TRUE;
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Cio2Config->PortCDCtleEnable = TRUE;
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Cio2Config->PortACtleCapValue = 0xE;
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Cio2Config->PortBCtleCapValue = 0xE;
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Cio2Config->PortCDCtleCapValue = 0xE;
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Cio2Config->PortACtleResValue = 0xD;
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Cio2Config->PortBCtleResValue = 0xD;
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Cio2Config->PortCDCtleResValue = 0xD;
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Cio2Config->PortAClkTrimValue = 0xA;
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Cio2Config->PortBClkTrimValue = 0xA;
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Cio2Config->PortCClkTrimValue = 0x9;
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Cio2Config->PortDClkTrimValue = 0xA;
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Cio2Config->PortADataTrimValue = 0xBBBB;
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Cio2Config->PortBDataTrimValue = 0xBBBB;
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Cio2Config->PortCDDataTrimValue = 0xCCCC;
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}
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/**
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Load Config block default
|
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@param[in] ConfigBlockPointer Pointer to config block
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**/
|
VOID
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LoadDmiConfigDefault (
|
IN VOID *ConfigBlockPointer
|
)
|
{
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PCH_DMI_CONFIG *DmiConfig;
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DmiConfig = ConfigBlockPointer;
|
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DEBUG ((DEBUG_INFO, "DmiConfig->Header.GuidHob.Name = %g\n", &DmiConfig->Header.GuidHob.Name));
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DEBUG ((DEBUG_INFO, "DmiConfig->Header.GuidHob.Header.HobLength = 0x%x\n", DmiConfig->Header.GuidHob.Header.HobLength));
|
|
/********************************
|
DMI related settings
|
********************************/
|
DmiConfig->DmiAspm = TRUE;
|
}
|
|
/**
|
Load Config block default
|
|
@param[in] ConfigBlockPointer Pointer to config block
|
**/
|
VOID
|
LoadFlashProtectionConfigDefault (
|
IN VOID *ConfigBlockPointer
|
)
|
{
|
PCH_FLASH_PROTECTION_CONFIG *FlashProtectionConfig;
|
FlashProtectionConfig = ConfigBlockPointer;
|
|
DEBUG ((DEBUG_INFO, "FlashProtectionConfig->Header.GuidHob.Name = %g\n", &FlashProtectionConfig->Header.GuidHob.Name));
|
DEBUG ((DEBUG_INFO, "FlashProtectionConfig->Header.GuidHob.Header.HobLength = 0x%x\n", FlashProtectionConfig->Header.GuidHob.Header.HobLength));
|
}
|
|
/**
|
Load Config block default
|
|
@param[in] ConfigBlockPointer Pointer to config block
|
**/
|
VOID
|
LoadHdAudioConfigDefault (
|
IN VOID *ConfigBlockPointer
|
)
|
{
|
PCH_HDAUDIO_CONFIG *HdaAudioConfig;
|
HdaAudioConfig = ConfigBlockPointer;
|
|
DEBUG ((DEBUG_INFO, "HdaAudioConfig->Header.GuidHob.Name = %g\n", &HdaAudioConfig->Header.GuidHob.Name));
|
DEBUG ((DEBUG_INFO, "HdaAudioConfig->Header.GuidHob.Header.HobLength = 0x%x\n", HdaAudioConfig->Header.GuidHob.Header.HobLength));
|
|
/********************************
|
HD-Audio configuration
|
********************************/
|
HdaAudioConfig->Enable = PCH_HDAUDIO_AUTO;
|
HdaAudioConfig->DspEnable = TRUE;
|
HdaAudioConfig->HdAudioLinkFrequency = PchHdaLinkFreq24MHz;
|
HdaAudioConfig->IDispLinkFrequency = PchHdaLinkFreq96MHz;
|
HdaAudioConfig->ResetWaitTimer = 600; // Must be at least 521us (25 frames)
|
HdaAudioConfig->DspEndpointDmic = PchHdaDmic4chArray;
|
}
|
|
/**
|
Load Config block default
|
|
@param[in] ConfigBlockPointer Pointer to config block
|
**/
|
VOID
|
LoadInterruptConfigDefault (
|
IN VOID *ConfigBlockPointer
|
)
|
{
|
UINT8 IntConfigTableEntries;
|
PCH_INTERRUPT_CONFIG *InterruptConfig;
|
InterruptConfig = ConfigBlockPointer;
|
|
DEBUG ((DEBUG_INFO, "InterruptConfig->Header.GuidHob.Name = %g\n", &InterruptConfig->Header.GuidHob.Name));
|
DEBUG ((DEBUG_INFO, "InterruptConfig->Header.GuidHob.Header.HobLength = 0x%x\n", InterruptConfig->Header.GuidHob.Header.HobLength));
|
|
/********************************
|
Interrupt Configuration
|
********************************/
|
IntConfigTableEntries = sizeof (mDevIntConfig) / sizeof (PCH_DEVICE_INTERRUPT_CONFIG);
|
ASSERT (IntConfigTableEntries <= PCH_MAX_DEVICE_INTERRUPT_CONFIG);
|
InterruptConfig->NumOfDevIntConfig = IntConfigTableEntries;
|
CopyMem (
|
InterruptConfig->DevIntConfig,
|
mDevIntConfig,
|
sizeof (mDevIntConfig)
|
);
|
if (GetPchSeries () == PchLp) {
|
CopyMem (
|
&(InterruptConfig->DevIntConfig[IntConfigTableEntries]),
|
mLpOnlyDevIntConfig,
|
sizeof (mLpOnlyDevIntConfig)
|
);
|
InterruptConfig->NumOfDevIntConfig += (sizeof (mLpOnlyDevIntConfig) / sizeof (PCH_DEVICE_INTERRUPT_CONFIG));
|
}
|
|
ASSERT ((sizeof (mPxRcConfig) / sizeof (UINT8)) <= PCH_MAX_PXRC_CONFIG);
|
CopyMem (
|
InterruptConfig->PxRcConfig,
|
mPxRcConfig,
|
sizeof (mPxRcConfig)
|
);
|
|
InterruptConfig->GpioIrqRoute = 14;
|
InterruptConfig->SciIrqSelect = 9;
|
InterruptConfig->TcoIrqSelect = 9;
|
}
|
|
/**
|
Load Config block default
|
|
@param[in] ConfigBlockPointer Pointer to config block
|
**/
|
VOID
|
LoadIshConfigDefault (
|
IN VOID *ConfigBlockPointer
|
)
|
{
|
PCH_ISH_CONFIG *IshConfig;
|
IshConfig = ConfigBlockPointer;
|
|
DEBUG ((DEBUG_INFO, "IshConfig->Header.GuidHob.Name = %g\n", &IshConfig->Header.GuidHob.Name));
|
DEBUG ((DEBUG_INFO, "IshConfig->Header.GuidHob.Header.HobLength = 0x%x\n", IshConfig->Header.GuidHob.Header.HobLength));
|
|
/********************************
|
ISH Configuration
|
********************************/
|
IshConfig->Enable = TRUE;
|
}
|
|
/**
|
Load Config block default
|
|
@param[in] ConfigBlockPointer Pointer to config block
|
**/
|
VOID
|
LoadLanConfigDefault (
|
IN VOID *ConfigBlockPointer
|
)
|
{
|
PCH_LAN_CONFIG *LanConfig;
|
LanConfig = ConfigBlockPointer;
|
|
DEBUG ((DEBUG_INFO, "LanConfig->Header.GuidHob.Name = %g\n", &LanConfig->Header.GuidHob.Name));
|
DEBUG ((DEBUG_INFO, "LanConfig->Header.GuidHob.Header.HobLength = 0x%x\n", LanConfig->Header.GuidHob.Header.HobLength));
|
|
/********************************
|
Lan configuration
|
********************************/
|
LanConfig->Enable = TRUE;
|
LanConfig->LtrEnable = TRUE;
|
}
|
|
/**
|
Load Config block default
|
|
@param[in] ConfigBlockPointer Pointer to config block
|
**/
|
VOID
|
LoadLockDownConfigDefault (
|
IN VOID *ConfigBlockPointer
|
)
|
{
|
PCH_LOCK_DOWN_CONFIG *LockDownConfig;
|
LockDownConfig = ConfigBlockPointer;
|
|
DEBUG ((DEBUG_INFO, "LockDownConfig->Header.GuidHob.Name = %g\n", &LockDownConfig->Header.GuidHob.Name));
|
DEBUG ((DEBUG_INFO, "LockDownConfig->Header.GuidHob.Header.HobLength = 0x%x\n", LockDownConfig->Header.GuidHob.Header.HobLength));
|
|
/********************************
|
Lockdown configuration
|
********************************/
|
LockDownConfig->GlobalSmi = TRUE;
|
//
|
// PCH BIOS Spec Flash Security Recommendations,
|
// Intel strongly recommends that BIOS sets the BIOS Interface Lock Down bit. Enabling this bit
|
// will mitigate malicious software attempts to replace the system BIOS option ROM with its own code.
|
// Here we always enable this as a Policy.
|
//
|
LockDownConfig->BiosInterface = TRUE;
|
LockDownConfig->RtcLock = TRUE;
|
|
//
|
// Enable BIOS region lock in SPI
|
//
|
LockDownConfig->BiosLock = TRUE;
|
LockDownConfig->SpiEiss = TRUE;
|
}
|
|
/**
|
Load Config block default
|
|
@param[in] ConfigBlockPointer Pointer to config block
|
**/
|
VOID
|
LoadP2sbConfigDefault (
|
IN VOID *ConfigBlockPointer
|
)
|
{
|
PCH_P2SB_CONFIG *P2sbConfig;
|
P2sbConfig = ConfigBlockPointer;
|
|
DEBUG ((DEBUG_INFO, "P2sbConfig->Header.GuidHob.Name = %g\n", &P2sbConfig->Header.GuidHob.Name));
|
DEBUG ((DEBUG_INFO, "P2sbConfig->Header.GuidHob.Header.HobLength = 0x%x\n", P2sbConfig->Header.GuidHob.Header.HobLength));
|
}
|
|
/**
|
Load Config block default
|
|
@param[in] ConfigBlockPointer Pointer to config block
|
**/
|
VOID
|
LoadPmConfigDefault (
|
IN VOID *ConfigBlockPointer
|
)
|
{
|
PCH_PM_CONFIG *PmConfig;
|
PmConfig = ConfigBlockPointer;
|
|
DEBUG ((DEBUG_INFO, "PmConfig->Header.GuidHob.Name = %g\n", &PmConfig->Header.GuidHob.Name));
|
DEBUG ((DEBUG_INFO, "PmConfig->Header.GuidHob.Header.HobLength = 0x%x\n", PmConfig->Header.GuidHob.Header.HobLength));
|
|
/********************************
|
MiscPm Configuration
|
********************************/
|
PmConfig->MeWakeSts = TRUE;
|
PmConfig->WolOvrWkSts = TRUE;
|
|
PmConfig->WakeConfig.WolEnableOverride = TRUE;
|
PmConfig->WakeConfig.LanWakeFromDeepSx = TRUE;
|
|
PmConfig->PchSlpS3MinAssert = PchSlpS350ms;
|
PmConfig->PchSlpS4MinAssert = PchSlpS44s;
|
PmConfig->PchSlpSusMinAssert = PchSlpSus4s;
|
PmConfig->PchSlpAMinAssert = PchSlpA2s;
|
|
PmConfig->PmcReadDisable = TRUE;
|
PmConfig->SlpLanLowDc = TRUE;
|
PmConfig->LpcClockRun = TRUE;
|
PmConfig->SlpS0Enable = TRUE;
|
PmConfig->SlpS0VmEnable = TRUE;
|
}
|
|
/**
|
Load Config block default
|
|
@param[in] ConfigBlockPointer Pointer to config block
|
**/
|
VOID
|
LoadPort61ConfigDefault (
|
IN VOID *ConfigBlockPointer
|
)
|
{
|
PCH_PORT61H_SMM_CONFIG *Port61Config;
|
Port61Config = ConfigBlockPointer;
|
|
DEBUG ((DEBUG_INFO, "Port61Config->Header.GuidHob.Name = %g\n", &Port61Config->Header.GuidHob.Name));
|
DEBUG ((DEBUG_INFO, "Port61Config->Header.GuidHob.Header.HobLength = 0x%x\n", Port61Config->Header.GuidHob.Header.HobLength));
|
|
/********************************
|
Port 61h emulation
|
********************************/
|
Port61Config->Enable = TRUE;
|
}
|
|
/**
|
Load Config block default
|
|
@param[in] ConfigBlockPointer Pointer to config block
|
**/
|
VOID
|
LoadScsConfigDefault (
|
IN VOID *ConfigBlockPointer
|
)
|
{
|
PCH_SCS_CONFIG *ScsConfig;
|
ScsConfig = ConfigBlockPointer;
|
|
DEBUG ((DEBUG_INFO, "ScsConfig->Header.GuidHob.Name = %g\n", &ScsConfig->Header.GuidHob.Name));
|
DEBUG ((DEBUG_INFO, "ScsConfig->Header.GuidHob.Header.HobLength = 0x%x\n", ScsConfig->Header.GuidHob.Header.HobLength));
|
|
/********************************
|
SCS Configuration
|
********************************/
|
ScsConfig->ScsEmmcEnabled = TRUE;
|
ScsConfig->ScsSdSwitch = PchScsSdcardMode;
|
ScsConfig->ScsEmmcHs400DriverStrength = DriverStrength40Ohm;
|
}
|
|
/**
|
Load Config block default
|
|
@param[in] ConfigBlockPointer Pointer to config block
|
**/
|
VOID
|
LoadSerialIoConfigDefault (
|
IN VOID *ConfigBlockPointer
|
)
|
{
|
UINTN Index;
|
PCH_SERIAL_IO_CONFIG *SerialIoConfig;
|
SerialIoConfig = ConfigBlockPointer;
|
|
DEBUG ((DEBUG_INFO, "SerialIoConfig->Header.GuidHob.Name = %g\n", &SerialIoConfig->Header.GuidHob.Name));
|
DEBUG ((DEBUG_INFO, "SerialIoConfig->Header.GuidHob.Header.HobLength = 0x%x\n", SerialIoConfig->Header.GuidHob.Header.HobLength));
|
|
/********************************
|
SerialIo Configuration
|
********************************/
|
for (Index = 0; Index < PCH_SERIALIO_MAX_CONTROLLERS; Index++) {
|
SerialIoConfig->DevMode[Index] = PchSerialIoPci;
|
}
|
SerialIoConfig->Gpio = TRUE;
|
SerialIoConfig->DebugUartNumber = PcdGet8 (PcdSerialIoUartNumber);
|
}
|
|
/**
|
Load Config block default
|
|
@param[in] ConfigBlockPointer Pointer to config block
|
**/
|
VOID
|
LoadSerialIrqConfigDefault (
|
IN VOID *ConfigBlockPointer
|
)
|
{
|
PCH_LPC_SIRQ_CONFIG *SerialIrqConfig;
|
SerialIrqConfig = ConfigBlockPointer;
|
|
DEBUG ((DEBUG_INFO, "SerialIrqConfig->Header.GuidHob.Name = %g\n", &SerialIrqConfig->Header.GuidHob.Name));
|
DEBUG ((DEBUG_INFO, "SerialIrqConfig->Header.GuidHob.Header.HobLength = 0x%x\n", SerialIrqConfig->Header.GuidHob.Header.HobLength));
|
|
/********************************
|
Serial IRQ Configuration
|
********************************/
|
SerialIrqConfig->SirqEnable = TRUE;
|
SerialIrqConfig->SirqMode = PchQuietMode;
|
SerialIrqConfig->StartFramePulse = PchSfpw4Clk;
|
}
|
|
/**
|
Load Config block default
|
|
@param[in] ConfigBlockPointer Pointer to config block
|
**/
|
VOID
|
LoadSpiConfigDefault (
|
IN VOID *ConfigBlockPointer
|
)
|
{
|
PCH_SPI_CONFIG *SpiConfig;
|
SpiConfig = ConfigBlockPointer;
|
|
DEBUG ((DEBUG_INFO, "SpiConfig->Header.GuidHob.Name = %g\n", &SpiConfig->Header.GuidHob.Name));
|
DEBUG ((DEBUG_INFO, "SpiConfig->Header.GuidHob.Header.HobLength = 0x%x\n", SpiConfig->Header.GuidHob.Header.HobLength));
|
}
|
|
/**
|
Load Config block default
|
|
@param[in] ConfigBlockPointer Pointer to config block
|
**/
|
VOID
|
LoadThermalConfigDefault (
|
IN VOID *ConfigBlockPointer
|
)
|
{
|
PCH_THERMAL_CONFIG *ThermalConfig;
|
ThermalConfig = ConfigBlockPointer;
|
|
DEBUG ((DEBUG_INFO, "ThermalConfig->Header.GuidHob.Name = %g\n", &ThermalConfig->Header.GuidHob.Name));
|
DEBUG ((DEBUG_INFO, "ThermalConfig->Header.GuidHob.Header.HobLength = 0x%x\n", ThermalConfig->Header.GuidHob.Header.HobLength));
|
|
/********************************
|
Thermal configuration.
|
********************************/
|
ThermalConfig->ThermalDeviceEnable = 1;
|
ThermalConfig->TsmicLock = TRUE;
|
ThermalConfig->TTLevels.SuggestedSetting = TRUE;
|
ThermalConfig->TTLevels.PchCrossThrottling = TRUE;
|
ThermalConfig->DmiHaAWC.SuggestedSetting = TRUE;
|
ThermalConfig->SataTT.SuggestedSetting = TRUE;
|
ThermalConfig->MemoryThrottling.TsGpioPinSetting[TsGpioC].PmsyncEnable = TRUE;
|
ThermalConfig->MemoryThrottling.TsGpioPinSetting[TsGpioC].C0TransmitEnable = TRUE;
|
ThermalConfig->MemoryThrottling.TsGpioPinSetting[TsGpioD].PmsyncEnable = TRUE;
|
ThermalConfig->MemoryThrottling.TsGpioPinSetting[TsGpioD].C0TransmitEnable = TRUE;
|
}
|
|
/**
|
Load Config block default
|
|
@param[in] ConfigBlockPointer Pointer to config block
|
**/
|
VOID
|
LoadUsbConfigDefault (
|
IN VOID *ConfigBlockPointer
|
)
|
{
|
UINTN PortIndex;
|
PCH_USB_CONFIG *UsbConfig;
|
UsbConfig = ConfigBlockPointer;
|
|
DEBUG ((DEBUG_INFO, "UsbConfig->Header.GuidHob.Name = %g\n", &UsbConfig->Header.GuidHob.Name));
|
DEBUG ((DEBUG_INFO, "UsbConfig->Header.GuidHob.Header.HobLength = 0x%x\n", UsbConfig->Header.GuidHob.Header.HobLength));
|
|
/********************************
|
USB related configuration
|
********************************/
|
for (PortIndex = 0; PortIndex < GetPchXhciMaxUsb2PortNum (); PortIndex++) {
|
UsbConfig->PortUsb20[PortIndex].Enable = TRUE;
|
}
|
|
for (PortIndex = 0; PortIndex < GetPchXhciMaxUsb3PortNum (); PortIndex++) {
|
UsbConfig->PortUsb30[PortIndex].Enable = TRUE;
|
}
|
//
|
// USB Port Over Current Pins mapping, please set as per board layout.
|
// Default is PchUsbOverCurrentPin0(0)
|
//
|
UsbConfig->PortUsb20[ 2].OverCurrentPin = PchUsbOverCurrentPin1;
|
UsbConfig->PortUsb20[ 3].OverCurrentPin = PchUsbOverCurrentPin1;
|
UsbConfig->PortUsb20[ 4].OverCurrentPin = PchUsbOverCurrentPin2;
|
UsbConfig->PortUsb20[ 5].OverCurrentPin = PchUsbOverCurrentPin2;
|
UsbConfig->PortUsb20[ 6].OverCurrentPin = PchUsbOverCurrentPin3;
|
UsbConfig->PortUsb20[ 7].OverCurrentPin = PchUsbOverCurrentPin3;
|
UsbConfig->PortUsb20[ 8].OverCurrentPin = PchUsbOverCurrentPin4;
|
UsbConfig->PortUsb20[ 9].OverCurrentPin = PchUsbOverCurrentPin4;
|
UsbConfig->PortUsb20[10].OverCurrentPin = PchUsbOverCurrentPin5;
|
UsbConfig->PortUsb20[11].OverCurrentPin = PchUsbOverCurrentPin5;
|
UsbConfig->PortUsb20[12].OverCurrentPin = PchUsbOverCurrentPin6;
|
UsbConfig->PortUsb20[13].OverCurrentPin = PchUsbOverCurrentPin6;
|
|
UsbConfig->PortUsb30[2].OverCurrentPin = PchUsbOverCurrentPin1;
|
UsbConfig->PortUsb30[3].OverCurrentPin = PchUsbOverCurrentPin1;
|
UsbConfig->PortUsb30[4].OverCurrentPin = PchUsbOverCurrentPin2;
|
UsbConfig->PortUsb30[5].OverCurrentPin = PchUsbOverCurrentPin2;
|
|
//
|
// Default values of USB2 AFE settings.
|
//
|
for (PortIndex = 0; PortIndex < PCH_H_XHCI_MAX_USB2_PORTS; PortIndex++) {
|
UsbConfig->PortUsb20[PortIndex].Afe.Petxiset = 3;
|
UsbConfig->PortUsb20[PortIndex].Afe.Txiset = 2;
|
UsbConfig->PortUsb20[PortIndex].Afe.Predeemp = 1;
|
UsbConfig->PortUsb20[PortIndex].Afe.Pehalfbit = 1;
|
}
|
|
//
|
// Enable/Disable SSIC support in the setup menu
|
//
|
for (PortIndex = 0; PortIndex < PCH_XHCI_MAX_SSIC_PORT_COUNT; PortIndex++) {
|
UsbConfig->SsicConfig.SsicPort[PortIndex].Enable = FALSE;
|
}
|
|
//
|
// xDCI configuration
|
//
|
UsbConfig->XdciConfig.Enable = FALSE;
|
}
|
|
/**
|
Load Espi Config block default
|
|
@param[in] ConfigBlockPointer Pointer to config block
|
**/
|
VOID
|
LoadEspiConfigDefault (
|
IN VOID *ConfigBlockPointer
|
)
|
{
|
PCH_ESPI_CONFIG *EspiConfig;
|
EspiConfig = ConfigBlockPointer;
|
|
DEBUG ((DEBUG_INFO, "EspiConfig->Header.GuidHob.Name = %g\n", &EspiConfig->Header.GuidHob.Name));
|
DEBUG ((DEBUG_INFO, "EspiConfig->Header.GuidHob.Header.HobLength = 0x%x\n", EspiConfig->Header.GuidHob.Header.HobLength));
|
|
/********************************
|
Espi configuration.
|
********************************/
|
EspiConfig->BmeMasterSlaveEnabled = TRUE;
|
}
|
|
static COMPONENT_BLOCK_ENTRY mPchIpBlocks [] = {
|
{&gPchGeneralConfigGuid, sizeof (PCH_GENERAL_CONFIG), PCH_GENERAL_CONFIG_REVISION, LoadPchGeneralConfigDefault},
|
{&gPcieRpConfigGuid, sizeof (PCH_PCIE_CONFIG), PCIE_RP_CONFIG_REVISION, LoadPcieRpConfigDefault},
|
{&gSataConfigGuid, sizeof (PCH_SATA_CONFIG), SATA_CONFIG_REVISION, LoadSataConfigDefault},
|
{&gIoApicConfigGuid, sizeof (PCH_IOAPIC_CONFIG), IOAPIC_CONFIG_REVISION, LoadIoApicConfigDefault},
|
{&gCio2ConfigGuid, sizeof (PCH_CIO2_CONFIG), CIO2_CONFIG_REVISION, LoadCio2ConfigDefault},
|
{&gDmiConfigGuid, sizeof (PCH_DMI_CONFIG), DMI_CONFIG_REVISION, LoadDmiConfigDefault},
|
{&gFlashProtectionConfigGuid, sizeof (PCH_FLASH_PROTECTION_CONFIG), FLASH_PROTECTION_CONFIG_REVISION, LoadFlashProtectionConfigDefault},
|
{&gHdAudioConfigGuid, sizeof (PCH_HDAUDIO_CONFIG), HDAUDIO_CONFIG_REVISION, LoadHdAudioConfigDefault},
|
{&gInterruptConfigGuid, sizeof (PCH_INTERRUPT_CONFIG), INTERRUPT_CONFIG_REVISION, LoadInterruptConfigDefault},
|
{&gIshConfigGuid, sizeof (PCH_ISH_CONFIG), ISH_CONFIG_REVISION, LoadIshConfigDefault},
|
{&gLanConfigGuid, sizeof (PCH_LAN_CONFIG), LAN_CONFIG_REVISION, LoadLanConfigDefault},
|
{&gLockDownConfigGuid, sizeof (PCH_LOCK_DOWN_CONFIG), LOCK_DOWN_CONFIG_REVISION, LoadLockDownConfigDefault},
|
{&gP2sbConfigGuid, sizeof (PCH_P2SB_CONFIG), P2SB_CONFIG_REVISION, LoadP2sbConfigDefault},
|
{&gPmConfigGuid, sizeof (PCH_PM_CONFIG), PM_CONFIG_REVISION, LoadPmConfigDefault},
|
{&gPort61ConfigGuid, sizeof (PCH_PORT61H_SMM_CONFIG), PORT_61_CONFIG_REVISION, LoadPort61ConfigDefault},
|
{&gScsConfigGuid, sizeof (PCH_SCS_CONFIG), SCS_CONFIG_REVISION, LoadScsConfigDefault},
|
{&gSerialIoConfigGuid, sizeof (PCH_SERIAL_IO_CONFIG), SERIAL_IO_CONFIG_REVISION, LoadSerialIoConfigDefault},
|
{&gSerialIrqConfigGuid, sizeof (PCH_LPC_SIRQ_CONFIG), SERIAL_IRQ_CONFIG_REVISION, LoadSerialIrqConfigDefault},
|
{&gSpiConfigGuid, sizeof (PCH_SPI_CONFIG), SPI_CONFIG_REVISION, LoadSpiConfigDefault},
|
{&gThermalConfigGuid, sizeof (PCH_THERMAL_CONFIG), THERMAL_CONFIG_REVISION, LoadThermalConfigDefault},
|
{&gUsbConfigGuid, sizeof (PCH_USB_CONFIG), USB_CONFIG_REVISION, LoadUsbConfigDefault},
|
{&gEspiConfigGuid, sizeof (PCH_ESPI_CONFIG), ESPI_CONFIG_REVISION, LoadEspiConfigDefault}
|
|
|
};
|
|
/**
|
Get PCH config block table total size.
|
|
@retval Size of PCH config block table
|
**/
|
UINT16
|
EFIAPI
|
PchGetConfigBlockTotalSize (
|
VOID
|
)
|
{
|
return GetComponentConfigBlockTotalSize (&mPchIpBlocks[0], sizeof (mPchIpBlocks) / sizeof (COMPONENT_BLOCK_ENTRY));
|
}
|
|
/**
|
PchAddConfigBlocks add all PCH config blocks.
|
|
@param[in] ConfigBlockTableAddress The pointer to add PCH config blocks
|
|
@retval EFI_SUCCESS The policy default is initialized.
|
@retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
|
**/
|
EFI_STATUS
|
EFIAPI
|
PchAddConfigBlocks (
|
IN VOID *ConfigBlockTableAddress
|
)
|
{
|
DEBUG ((DEBUG_INFO, "PCH AddConfigBlocks\n"));
|
|
return AddComponentConfigBlocks (ConfigBlockTableAddress, &mPchIpBlocks[0], sizeof (mPchIpBlocks) / sizeof (COMPONENT_BLOCK_ENTRY));
|
}
|
