/** @file
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USB policy
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _USB_CONFIG_H_
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#define _USB_CONFIG_H_
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#define USB_CONFIG_REVISION 2
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extern EFI_GUID gUsbConfigGuid;
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#pragma pack (push,1)
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///
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/// Overcurrent pins, the values match the setting of PCH EDS, please refer to PCH EDS for more details
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///
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typedef enum {
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PchUsbOverCurrentPin0 = 0,
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PchUsbOverCurrentPin1,
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PchUsbOverCurrentPin2,
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PchUsbOverCurrentPin3,
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PchUsbOverCurrentPin4,
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PchUsbOverCurrentPin5,
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PchUsbOverCurrentPin6,
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PchUsbOverCurrentPin7,
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PchUsbOverCurrentPinSkip,
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PchUsbOverCurrentPinMax
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} PCH_USB_OVERCURRENT_PIN;
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///
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/// The location of the USB connectors. This information is use to decide eye diagram tuning value for Usb 2.0 motherboard trace.
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///
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enum PCH_USB_PORT_LOCATION{
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PchUsbPortLocationBackPanel = 0,
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PchUsbPortLocationFrontPanel,
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PchUsbPortLocationDock,
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PchUsbPortLocationMiniPciE,
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PchUsbPortLocationFlex,
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PchUsbPortLocationInternalTopology,
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PchUsbPortLocationSkip,
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PchUsbPortLocationMax
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};
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/**
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This structure configures per USB2 AFE settings.
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It allows to setup the port parameters.
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**/
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typedef struct {
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/** Per Port HS Preemphasis Bias (PERPORTPETXISET)
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000b - 0mV
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001b - 11.25mV
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010b - 16.9mV
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011b - 28.15mV
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100b - 28.15mV
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101b - 39.35mV
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110b - 45mV
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111b - 56.3mV
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**/
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UINT8 Petxiset;
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/** Per Port HS Transmitter Bias (PERPORTTXISET)
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000b - 0mV
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001b - 11.25mV
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010b - 16.9mV
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011b - 28.15mV
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100b - 28.15mV
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101b - 39.35mV
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110b - 45mV
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111b - 56.3mV
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**/
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UINT8 Txiset;
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/**
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Per Port HS Transmitter Emphasis (IUSBTXEMPHASISEN)
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00b - Emphasis OFF
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01b - De-emphasis ON
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10b - Pre-emphasis ON
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11b - Pre-emphasis & De-emphasis ON
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**/
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UINT8 Predeemp;
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/**
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Per Port Half Bit Pre-emphasis (PERPORTTXPEHALF)
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1b - half-bit pre-emphasis
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0b - full-bit pre-emphasis
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**/
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UINT8 Pehalfbit;
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} PCH_USB20_AFE;
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/**
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This structure configures per USB2 port physical settings.
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It allows to setup the port location and port length, and configures the port strength accordingly.
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**/
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typedef struct {
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UINT32 Enable : 1; ///< 0: Disable; <b>1: Enable</b>.
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UINT32 RsvdBits0 : 31; ///< Reserved bits
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/**
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These members describe the specific over current pin number of USB 2.0 Port N.
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It is SW's responsibility to ensure that a given port's bit map is set only for
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one OC pin Description. USB2 and USB3 on the same combo Port must use the same
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OC pin (see: PCH_USB_OVERCURRENT_PIN).
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**/
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UINT8 OverCurrentPin;
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UINT8 Rsvd0[3]; ///< Reserved bytes, align to multiple 4.
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PCH_USB20_AFE Afe; ///< USB2 AFE settings
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UINT32 Rsvd1[1]; ///< Reserved bytes
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} PCH_USB20_PORT_CONFIG;
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/**
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This structure describes whether the USB3 Port N of PCH is enabled by platform modules.
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**/
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typedef struct {
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UINT32 Enable : 1; ///< 0: Disable; <b>1: Enable</b>.
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UINT32 RsvdBits0 : 31; ///< Reserved bits
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/**
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These members describe the specific over current pin number of USB 3.0 Port N.
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It is SW's responsibility to ensure that a given port's bit map is set only for
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one OC pin Description. USB2 and USB3 on the same combo Port must use the same
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OC pin (see: PCH_USB_OVERCURRENT_PIN).
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**/
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UINT8 OverCurrentPin;
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UINT8 Rsvd0[3]; ///< Reserved bytes, align to multiple 4
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UINT32 HsioTxDeEmphEnable : 1; ///< Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment, <b>0: Disable</b>; 1: Enable.
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/**
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USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting (ow2tapgen2deemph3p5)
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HSIO_TX_DWORD5[21:16]
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<b>Default = 29h</b> (approximately -3.5dB De-Emphasis)
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**/
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UINT32 HsioTxDeEmph : 6;
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UINT32 HsioTxDownscaleAmpEnable : 1; ///< Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, <b>0: Disable</b>; 1: Enable.
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/**
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USB 3.0 TX Output Downscale Amplitude Adjustment (orate01margin)
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HSIO_TX_DWORD8[21:16]
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<b>Default = 00h</b>
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**/
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UINT32 HsioTxDownscaleAmp : 6;
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UINT32 RsvdBits1 : 18; ///< Reserved bits
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UINT32 Rsvd1[1]; ///< Reserved bytes
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} PCH_USB30_PORT_CONFIG;
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#define PCH_XHCI_MODE_OFF 0
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#define PCH_XHCI_MODE_ON 1
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/**
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These members describe some settings which are related to the SSIC ports.
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**/
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typedef struct {
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/**
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0: Disable; <b>1: Enable</b> SSIC support.
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**/
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UINT32 Enable : 1;
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UINT32 RsvdBits1 : 31;
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} PCH_XHCI_SSIC_PORT;
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/**
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These members describe some settings which are related to the SSIC ports.
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**/
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typedef struct {
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PCH_XHCI_SSIC_PORT SsicPort[PCH_XHCI_MAX_SSIC_PORT_COUNT];
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} PCH_SSIC_CONFIG;
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/**
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The PCH_XDCI_CONFIG block describes the configurations
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of the xDCI Usb Device controller.
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**/
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typedef struct {
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/**
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This member describes whether or not the xDCI controller should be enabled.
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0: Disable; <b>1: Enable</b>.
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**/
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UINT32 Enable : 1;
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UINT32 RsvdBits0 : 31; ///< Reserved bits
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} PCH_XDCI_CONFIG;
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/**
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This member describes the expected configuration of the PCH USB controllers,
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Platform modules may need to refer Setup options, schematic, BIOS specification
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to update this field.
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The Usb20OverCurrentPins and Usb30OverCurrentPins field must be updated by referring
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the schematic.
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<b>Revision 1</b>:
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- Initial version.
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<b>Revision 2</b>:
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- Added DelayPdoProgramming policy option.
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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/**
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This policy will disable XHCI compliance mode on all ports. Complicance Mode should be default enabled.
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For the platform that support USB Type-C, it can disable Compliance Mode, and enable Compliance Mode when testing.
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<b>0:Disable</b> , 1: Enable
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**/
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UINT32 DisableComplianceMode : 1;
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/**
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This policy option if set will move Port Disable Override register programming to ReadyToBoot event during DXE phase.
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If not enabled it will program Port Disable Override register in PEI phase during PCH initialization
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<b>0: Program in PEI phase </b>, 1: Program in DXE phase
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**/
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UINT32 DelayPdoProgramming : 1;
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UINT32 RsvdBits0 : 30; ///< Reserved bits
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/**
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These members describe whether the USB2 Port N of PCH is enabled by platform modules.
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Panel and Dock are used to describe the layout of USB port. Panel is only available for Desktop PCH.
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Dock is only available for Mobile LPT.
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**/
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PCH_USB20_PORT_CONFIG PortUsb20[PCH_MAX_USB2_PORTS];
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/**
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These members describe whether the USB3 Port N of PCH is enabled by platform modules.
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**/
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PCH_USB30_PORT_CONFIG PortUsb30[PCH_MAX_USB3_PORTS];
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/**
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This member describes whether or not the xDCI controller should be enabled.
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**/
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PCH_XDCI_CONFIG XdciConfig;
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/**
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These members describe some settings which are related to the SSIC ports.
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**/
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PCH_SSIC_CONFIG SsicConfig;
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} PCH_USB_CONFIG;
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#pragma pack (pop)
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#endif // _USB_CONFIG_H_
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