/** @file
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Header file for PchPsfPrivateLib.
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Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCH_PSF_PRIVATE_LIB_H_
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#define _PCH_PSF_PRIVATE_LIB_H_
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#include <Library/PchPcrLib.h>
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#include <Register/PchRegsPcr.h>
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//
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// Structure for storing data on both PSF SideBand Port ID and
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// PSF port register offset for specific device
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//
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typedef struct {
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PCH_SBI_PID PsfPid;
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UINT16 RegBase;
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} PSF_PORT;
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/**
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Disable device at PSF level
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Method not for bridges (e.g. PCIe Root Port)
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@param[in] PsfPort PSF PORT data structure
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**/
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VOID
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PsfDisableDevice (
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IN PSF_PORT PsfPort
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);
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/**
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Enable device at PSF level
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Method not for bridges (e.g. PCIe Root Port)
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@param[in] PsfPort PSF PORT data structure
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**/
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VOID
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PsfEnableDevice (
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IN PSF_PORT PsfPort
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);
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/**
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Hide PciCfgSpace of device at PSF level
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Method not for bridges (e.g. PCIe Root Port)
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@param[in] PsfPort PSF PORT data structure
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**/
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VOID
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PsfHideDevice (
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IN PSF_PORT PsfPort
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);
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/**
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Unhide PciCfgSpace of device at PSF level
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Method not for bridges (e.g. PCIe Root Port)
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@param[in] PsfPort PSF PORT data structure
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**/
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VOID
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PsfUnhideDevice (
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IN PSF_PORT PsfPort
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);
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/**
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Disable device BARs at PSF level
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Method not for bridges (e.g. PCIe Root Port)
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@param[in] PsfPort PSF PORT data structure
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@param[in] BarDisMask BIT0-BAR0, BIT1-BAR1,...
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Mask corresponds to 32bit wide BARs
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**/
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VOID
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PsfDisableDeviceBar (
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IN PSF_PORT PsfPort,
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IN UINT32 BarDisMask
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);
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/**
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Enable device BARs at PSF level
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Method not for bridges (e.g. PCIe Root Port)
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@param[in] PsfPort PSF PORT data structure
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@param[in] BarEnMask BIT0-BAR0, BIT1-BAR1,...
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Mask corresponds to 32bit wide BARs
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**/
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VOID
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PsfEnableDeviceBar (
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IN PSF_PORT PsfPort,
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IN UINT32 BarEnMask
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);
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/**
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Return PSF_PORT for SerialIO I2C device
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@param[in] I2cNum Serial IO I2C device (I2C0, I2C1, ....)
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@retval PsfPort PSF PORT structure for SerialIO I2C device
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**/
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PSF_PORT
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PsfSerialIoI2cPort (
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IN UINT32 I2cNum
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);
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/**
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Return PSF_PORT for SerialIO SPI device
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@param[in] SpiNum Serial IO SPI device (SPI0, SPI1, ....)
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@retval PsfPort PSF PORT structure for SerialIO SPI device
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**/
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PSF_PORT
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PsfSerialIoSpiPort (
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IN UINT32 SpiNum
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);
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/**
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Return PSF_PORT for SerialIO UART device
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@param[in] UartNum Serial IO UART device (UART0, UART1, ....)
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@retval PsfPort PSF PORT structure for SerialIO UART device
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**/
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PSF_PORT
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PsfSerialIoUartPort (
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IN UINT32 UartNum
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);
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/**
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This procedure will set BARx value for TraceHub ACPI device at PSF level
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@param[in] BarNum BAR Number (0:BAR0, 1:BAR1)
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@param[in] BarValue 32bit BAR value
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**/
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VOID
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PsfSetTraceHubAcpiDeviceBarValue (
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IN UINT8 BarNum,
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IN UINT32 BarValue
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);
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/**
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This procedure will enable MSE for TraceHub ACPI device at PSF level
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**/
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VOID
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PsfEnableTraceHubAcpiDeviceMemorySpace (
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VOID
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);
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/**
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Enable HECI device at PSF level
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@param[in] HeciDevice HECIx Device (HECI1-4)
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**/
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VOID
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PsfEnableHeciDevice (
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IN UINT8 HeciDevice
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);
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/**
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Disable HECI device at PSF level
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@param[in] HeciDevice HECIx Device (HECI1-4)
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**/
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VOID
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PsfDisableHeciDevice (
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IN UINT8 HeciDevice
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);
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/**
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Disable IDER device at PSF level
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**/
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VOID
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PsfDisableIderDevice (
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VOID
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);
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/**
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Enable SOL device at PSF level
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**/
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VOID
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PsfEnableSolDevice (
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VOID
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);
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/**
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Disable SOL device at PSF level
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**/
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VOID
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PsfDisableSolDevice (
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VOID
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);
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/**
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Set PMC ABASE value in PSF
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@param[in] Address Address for ACPI base.
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**/
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VOID
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PsfSetPmcAbase (
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IN UINT16 Address
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);
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/**
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Get PMC ABASE value from PSF
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@retval Address Address for ACPI base.
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**/
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UINT16
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PsfGetPmcAbase (
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VOID
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);
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/**
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Get PMC PWRMBASE value from PSF
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@retval Address Address for PWRM base.
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**/
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UINT32
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PsfGetPmcPwrmBase (
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VOID
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);
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/**
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Hide Cnvi WiFi device's PciCfgSpace at PSF level
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**/
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VOID
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PsfHideCnviWifiDevice (
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VOID
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);
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/**
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Disable Cnvi Wifi device at PSF level
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**/
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VOID
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PsfDisableCnviWifiDevice (
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VOID
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);
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/**
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Disable HDAudio device at PSF level
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**/
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VOID
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PsfDisableHdaDevice (
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VOID
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);
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/**
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Disable xDCI device at PSF level
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**/
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VOID
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PsfDisableXdciDevice (
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VOID
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);
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/**
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Disable xHCI device at PSF level
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**/
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VOID
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PsfDisableXhciDevice (
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VOID
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);
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/**
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Disable xHCI VTIO Phantom device at PSF level
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**/
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VOID
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PsfDisableXhciVtioDevice (
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VOID
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);
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/**
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Disable SATA device at PSF level
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@param[in] SataCtrlIndex SATA controller index
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**/
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VOID
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PsfDisableSataDevice (
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IN UINT32 SataCtrlIndex
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);
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/**
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Return PSF_PORT for SCS eMMC device
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@retval PsfPort PSF PORT structure for SCS eMMC device
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**/
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PSF_PORT
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PsfScsEmmcPort (
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VOID
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);
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/**
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Return PSF_PORT for SCS SD Card device
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@retval PsfPort PSF PORT structure for SCS SD Card device
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**/
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PSF_PORT
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PsfScsSdCardPort (
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VOID
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);
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/**
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Return PSF_PORT for SCS UFS device
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@param[in] UfsNum UFS Device
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@retval PsfPort PSF PORT structure for SCS UFS device
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**/
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PSF_PORT
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PsfScsUfsPort (
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IN UINT32 UfsNum
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);
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/**
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Disable ISH device at PSF level
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**/
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VOID
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PsfDisableIshDevice (
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VOID
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);
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/**
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Disable ISH BAR1 at PSF level
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**/
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VOID
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PsfDisableIshBar1 (
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VOID
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);
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/**
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Disable GbE device at PSF level
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**/
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VOID
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PsfDisableGbeDevice (
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VOID
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);
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/**
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Disable SMBUS device at PSF level
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**/
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VOID
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PsfDisableSmbusDevice (
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VOID
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);
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/**
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Disable TraceHub ACPI devices at PSF level
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**/
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VOID
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PsfDisableTraceHubAcpiDevice (
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VOID
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);
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/**
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Hide TraceHub ACPI devices PciCfgSpace at PSF level
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**/
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VOID
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PsfHideTraceHubAcpiDevice (
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VOID
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);
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/**
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This procedure will hide TraceHub PciCfgSpace at PSF level
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**/
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VOID
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PsfHideTraceHubDevice (
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VOID
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);
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/**
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This procedure will unhide TraceHub PciCfgSpace at PSF level
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**/
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VOID
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PsfUnhideTraceHubDevice (
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VOID
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);
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/**
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This procedure will disable TraceHub device at PSF level
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**/
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VOID
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PsfDisableTraceHubDevice (
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VOID
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);
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/**
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Configures rootspace 3 bus number for PCIe IMR use
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@param[in] Rs3Bus bus number
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**/
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VOID
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PsfSetRs3Bus (
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UINT8 Rs3Bus
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);
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/**
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Disable PCIe Root Port at PSF level
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@param[in] RpIndex PCIe Root Port Index (0 based)
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**/
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VOID
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PsfDisablePcieRootPort (
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IN UINT32 RpIndex
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);
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/**
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Program PSF grant counts for SATA
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Call this before SATA ports are accessed for enumeration
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**/
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VOID
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PsfConfigureSataGrantCounts (
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VOID
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);
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typedef enum {
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PsfPcieCtrl4x1,
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PsfPcieCtrl1x2_2x1,
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PsfPcieCtrl2x2,
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PsfPcieCtrl1x4
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} PSF_PCIE_CTRL_CONFIG;
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/**
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Program PSF grant counts for PCI express depending on controllers configuration
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@param[in] PsfPcieCtrlConfigTable Table with PCIe controllers configuration
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@param[in] NumberOfPcieControllers Number of PCIe controllers. This is also the size of PsfPcieCtrlConfig table
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**/
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VOID
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PsfConfigurePcieGrantCounts (
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IN PSF_PCIE_CTRL_CONFIG *PsfPcieCtrlConfigTable,
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IN UINT32 NumberOfPcieControllers
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);
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/**
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Program PSF EOI Multicast configuration for ITSS
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**/
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VOID
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PsfConfigurEoiForItss (
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VOID
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);
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/**
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This function enables EOI message forwarding in PSF for PCIe ports
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for cases where IOAPIC is present behind this root port.
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@param[in] RpIndex Root port index (0 based)
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@retval Status
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**/
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EFI_STATUS
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PsfConfigurEoiForPciePort (
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IN UINT32 RpIndex
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);
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//
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// Structure for PSF Port Destination ID
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//
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typedef union {
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UINT32 RegVal;
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struct {
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UINT32 ChannelId : 8; // Channel ID
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UINT32 PortId : 7; // Port ID
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UINT32 PortGroupId : 1; // Port Group ID
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UINT32 PsfId : 8; // PSF ID
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UINT32 Rsvd : 7; // Reserved
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UINT32 ChanMap : 1; // Channel map
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} Fields;
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} PSF_PORT_DEST_ID;
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/**
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PCIe PSF port destination ID (psf_id:port_group_id:port_id:channel_id)
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@param[in] RpIndex PCIe Root Port Index (0 based)
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@retval Destination ID
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**/
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PSF_PORT_DEST_ID
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PsfPcieDestinationId (
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IN UINT32 RpIndex
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);
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/**
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PSF early initialization.
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**/
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VOID
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PsfEarlyInit (
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VOID
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);
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/**
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Assign new function number for PCIe Port Number.
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@param[in] RpIndex PCIe Root Port Index (0 based)
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@param[in] NewFunction New Function number
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**/
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VOID
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PsfSetPcieFunction (
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IN UINT32 RpIndex,
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IN UINT32 NewFunction
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);
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/**
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This function enables PCIe Relaxed Order in PSF
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**/
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VOID
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PsfEnablePcieRelaxedOrder (
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VOID
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);
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/**
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Configure PSF power management.
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Must be called after all PSF configuration is completed.
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**/
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VOID
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PsfConfigurePowerManagement (
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VOID
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);
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/**
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Enable VTd support in PSF.
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**/
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VOID
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PchPsfEnableVtd (
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VOID
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);
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/**
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Disable PSF address-based peer-to-peer decoding.
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**/
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VOID
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PchPsfDisableP2pDecoding (
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VOID
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);
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/**
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Perform registers programming required for
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Management Component Transport Protocol Broadcast Cycle.
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Agent Destination Addresses are being programmed only when adequate
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PCIe root port controllers are function enabled.
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Function sets CSME PMT as a message broadcaster and programs the targets
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of the message in registers only if adequate PCIe root port controllers
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are function enabled. Conditionally, if the CPU PEG exist and is function
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enabled, DMI is also a target.
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**/
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VOID
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PsfConfigureMctpCycle (
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VOID
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);
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/**
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This procedure will hide PMC device at PSF level
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**/
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VOID
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PsfHidePmcDevice (
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VOID
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);
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/**
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This procedure will disable D3:F0 device at PSF level for PCH-LP
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**/
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VOID
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PsfDisableD3F0 (
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VOID
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);
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/**
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This procedure will disable PSF upstream completion tracking for HDAudio on PCH-LP
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**/
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VOID
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PsfDisableUpstreamCompletionTrackingForHda (
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VOID
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);
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#endif // _PCH_PSF_PRIVATE_LIB_H_
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