/** @file
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Header file for PchCycleDecodingLib.
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Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCH_CYCLE_DECODING_LIB_H_
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#define _PCH_CYCLE_DECODING_LIB_H_
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/**
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Set PCH TCO base address.
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This cycle decoding is allowed to set when DMIC.SRL is 0.
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Programming steps:
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1. set Smbus PCI offset 54h [8] to enable TCO base address.
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2. program Smbus PCI offset 50h [15:5] to TCO base address.
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3. set Smbus PCI offset 54h [8] to enable TCO base address.
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4. program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1] to [Smbus PCI offset 50h[15:5], 1].
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@param[in] Address Address for TCO base address.
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@retval EFI_SUCCESS Successfully completed.
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@retval EFI_INVALID_PARAMETER Invalid base address passed.
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**/
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EFI_STATUS
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PchTcoBaseSet (
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IN UINT16 Address
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);
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/**
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Get PCH TCO base address.
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@param[out] Address Address of TCO base address.
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@retval EFI_SUCCESS Successfully completed.
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@retval EFI_INVALID_PARAMETER Invalid pointer passed.
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**/
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EFI_STATUS
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PchTcoBaseGet (
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OUT UINT16 *Address
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);
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///
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/// structure of LPC general IO range register
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/// It contains base address, address mask, and enable status.
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///
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typedef struct {
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UINT32 BaseAddr :16;
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UINT32 Length :15;
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UINT32 Enable : 1;
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} PCH_LPC_GEN_IO_RANGE;
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#define PCH_LPC_GEN_IO_RANGE_MAX 4
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#define ESPI_CS1_GEN_IO_RANGE_MAX 1
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#define PCH_H_ESPI_GEN_IO_RANGE_MAX PCH_LPC_GEN_IO_RANGE_MAX // @deprecated. Keep it here for backward compatibility.
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///
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/// structure of LPC general IO range register list
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/// It lists all LPC general IO ran registers supported by PCH.
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///
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typedef struct {
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PCH_LPC_GEN_IO_RANGE Range[PCH_LPC_GEN_IO_RANGE_MAX];
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} PCH_LPC_GEN_IO_RANGE_LIST;
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/**
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Set PCH LPC/eSPI generic IO range.
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For generic IO range, the base address must align to 4 and less than 0xFFFF, and the length must be power of 2
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and less than or equal to 256. Moreover, the address must be length aligned.
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This function basically checks the address and length, which should not overlap with all other generic ranges.
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If no more generic range register available, it returns out of resource error.
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This cycle decoding is also required on DMI side
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Some IO ranges below 0x100 have fixed target. The target might be ITSS,RTC,LPC,PMC or terminated inside P2SB
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but all predefined and can't be changed. IO range below 0x100 will be rejected in this function except below ranges:
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0x00-0x1F,
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0x44-0x4B,
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0x54-0x5F,
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0x68-0x6F,
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0x80-0x8F,
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0xC0-0xFF
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Steps of programming generic IO range:
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1. Program LPC/eSPI PCI Offset 84h ~ 93h of Mask, Address, and Enable.
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2. Program LPC/eSPI Generic IO Range in DMI
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@param[in] Address Address for generic IO range base address.
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@param[in] Length Length of generic IO range.
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@retval EFI_SUCCESS Successfully completed.
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@retval EFI_INVALID_PARAMETER Invalid base address or length passed.
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@retval EFI_OUT_OF_RESOURCES No more generic range available.
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@retval EFI_UNSUPPORTED DMIC.SRL is set.
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**/
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EFI_STATUS
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PchLpcGenIoRangeSet (
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IN UINT16 Address,
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IN UINTN Length
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);
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/**
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Set PCH eSPI CS1# generic IO range decoding.
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For generic IO range, the base address must align to 4 and less than 0xFFFF, and the length must be power of 2
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and less than or equal to 256. Moreover, the address must be length aligned.
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This function basically checks the address and length, which should not overlap with all other generic ranges.
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If no more generic range register available, it returns out of resource error.
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This cycle decoding is also required on DMI side
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Some IO ranges below 0x100 have fixed target. The target might be ITSS,RTC,LPC,PMC or terminated inside P2SB
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but all predefined and can't be changed. IO range below 0x100 will be rejected in this function except below ranges:
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0x00-0x1F,
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0x44-0x4B,
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0x54-0x5F,
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0x68-0x6F,
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0x80-0x8F,
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0xC0-0xFF
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Steps of programming generic IO range:
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1. Program eSPI PCI Offset A4h (eSPI CS1#) of Mask, Address, and Enable.
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2. Program eSPI Generic IO Range in DMI
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@param[in] Address Address for generic IO range decoding.
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@param[in] Length Length of generic IO range.
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@retval EFI_SUCCESS Successfully completed.
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@retval EFI_INVALID_PARAMETER Invalid base address or length passed.
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@retval EFI_OUT_OF_RESOURCES No more generic range available.
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@retval EFI_UNSUPPORTED eSPI secondary slave not supported
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**/
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EFI_STATUS
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PchEspiCs1GenIoRangeSet (
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IN UINT16 Address,
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IN UINTN Length
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);
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/**
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Get PCH LPC/eSPI generic IO range list.
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This function returns a list of base address, length, and enable for all LPC/eSPI generic IO range registers.
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@param[out] LpcGenIoRangeList Return all LPC/eSPI generic IO range register status.
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@retval EFI_SUCCESS Successfully completed.
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@retval EFI_INVALID_PARAMETER Invalid base address passed.
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**/
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EFI_STATUS
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PchLpcGenIoRangeGet (
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OUT PCH_LPC_GEN_IO_RANGE_LIST *LpcGenIoRangeList
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);
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/**
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Get PCH eSPI CS1# generic IO range list.
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This function returns a list of base address, length, and enable for all eSPI CS1# generic IO range registers.
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@param[out] GenIoRangeList eSPI generic IO range registers.
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@retval EFI_SUCCESS Successfully completed.
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@retval EFI_INVALID_PARAMETER Invalid base address passed.
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@retval EFI_UNSUPPORTED eSPI secondary slave not supported
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**/
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EFI_STATUS
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PchEspiCs1GenIoRangeGet (
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OUT PCH_LPC_GEN_IO_RANGE_LIST *GenIoRangeList
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);
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/**
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Set PCH LPC/eSPI memory range decoding.
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This cycle decoding is required to be set on DMI side
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Programming steps:
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1. Program LPC PCI Offset 98h [0] to [0] to disable memory decoding first before changing base address.
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2. Program LPC PCI Offset 98h [31:16, 0] to [Address, 1].
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3. Program LPC Memory Range in DMI
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@param[in] Address Address for memory base address.
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@retval EFI_SUCCESS Successfully completed.
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@retval EFI_INVALID_PARAMETER Invalid base address or length passed.
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@retval EFI_OUT_OF_RESOURCES No more generic range available.
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@retval EFI_UNSUPPORTED DMIC.SRL is set.
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**/
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EFI_STATUS
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PchLpcMemRangeSet (
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IN UINT32 Address
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);
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/**
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Set PCH eSPI CS1# memory range decoding.
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This cycle decoding is required to be set on DMI side
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Programming steps:
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1. Program eSPI PCI Offset A8h (eSPI CS1#) [0] to [0] to disable memory decoding first before changing base address.
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2. Program eSPI PCI Offset A8h (eSPI CS1#) [31:16, 0] to [Address, 1].
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3. Program eSPI Memory Range in DMI
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@param[in] Address Address for memory for decoding.
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@retval EFI_SUCCESS Successfully completed.
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@retval EFI_INVALID_PARAMETER Invalid base address or length passed.
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@retval EFI_UNSUPPORTED eSPI secondary slave not supported
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**/
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EFI_STATUS
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PchEspiCs1MemRangeSet (
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IN UINT32 Address
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);
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/**
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@deprecated. Keep this for backward compatibility.
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It's replaced by PchEspiCs1MemRangeSet.
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**/
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EFI_STATUS
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PchEspiMemRange2Set (
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IN UINT32 Address
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);
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/**
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Get PCH LPC/eSPI memory range decoding address.
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@param[out] Address Address of LPC/eSPI memory decoding base address.
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@retval EFI_SUCCESS Successfully completed.
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@retval EFI_INVALID_PARAMETER Invalid base address passed.
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**/
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EFI_STATUS
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PchLpcMemRangeGet (
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OUT UINT32 *Address
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);
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/**
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Get PCH eSPI CS1# memory range decoding address.
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@param[out] Address Address of eSPI CS1# memory decoding base address.
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@retval EFI_SUCCESS Successfully completed.
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@retval EFI_INVALID_PARAMETER Invalid base address passed.
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@retval EFI_UNSUPPORTED eSPI secondary slave not supported
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**/
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EFI_STATUS
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PchEspiCs1MemRangeGet (
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OUT UINT32 *Address
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);
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/**
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Set PCH BIOS range deocding.
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This will check General Control and Status bit 10 (GCS.BBS) to identify SPI or LPC/eSPI and program BDE register accordingly.
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Please check EDS for detail of BiosDecodeEnable bit definition.
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bit 15: F8-FF Enable
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bit 14: F0-F8 Enable
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bit 13: E8-EF Enable
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bit 12: E0-E8 Enable
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bit 11: D8-DF Enable
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bit 10: D0-D7 Enable
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bit 9: C8-CF Enable
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bit 8: C0-C7 Enable
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bit 7: Legacy F Segment Enable
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bit 6: Legacy E Segment Enable
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bit 5: Reserved
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bit 4: Reserved
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bit 3: 70-7F Enable
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bit 2: 60-6F Enable
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bit 1: 50-5F Enable
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bit 0: 40-4F Enable
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This cycle decoding is allowed to set when DMIC.SRL is 0.
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Programming steps:
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1. if GCS.BBS is 0 (SPI), program SPI PCI offset D8h to BiosDecodeEnable.
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if GCS.BBS is 1 (LPC/eSPi), program LPC/eSPI PCI offset D8h to BiosDecodeEnable.
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2. program LPC/eSPI/SPI BIOS Decode Enable, PCR[DMI] + 2744h to the same value programmed in LPC/eSPI or SPI PCI Offset D8h.
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@param[in] BiosDecodeEnable Bios decode enable setting.
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@retval EFI_SUCCESS Successfully completed.
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**/
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EFI_STATUS
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PchBiosDecodeEnableSet (
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IN UINT16 BiosDecodeEnable
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);
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/**
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Set PCH LPC IO decode ranges.
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Program LPC I/O Decode Ranges, PCR[DMI] + 2770h[15:0] to the same value programmed in LPC offset 80h.
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Please check EDS for detail of Lpc IO decode ranges bit definition.
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Bit 12: FDD range
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Bit 9:8: LPT range
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Bit 6:4: ComB range
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Bit 2:0: ComA range
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@param[in] LpcIoDecodeRanges Lpc IO decode ranges bit settings.
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@retval EFI_SUCCESS Successfully completed.
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@retval EFI_UNSUPPORTED DMIC.SRL is set.
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**/
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EFI_STATUS
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PchLpcIoDecodeRangesSet (
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IN UINT16 LpcIoDecodeRanges
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);
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/**
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Set PCH LPC and eSPI CS0# IO enable decoding.
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Setup I/O Enables in DMI to the same value program in LPC/eSPI PCI offset 82h.
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Note: Bit[15:10] of the source decode register is Read-Only. The IO range indicated by the Enables field
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in LPC/eSPI PCI offset 82h[13:10] is always forwarded by DMI to subtractive agent for handling.
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Please check EDS for detail of LPC/eSPI IO decode ranges bit definition.
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@param[in] LpcIoEnableDecoding LPC IO enable decoding bit settings.
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@retval EFI_SUCCESS Successfully completed.
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@retval EFI_UNSUPPORTED DMIC.SRL is set.
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**/
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EFI_STATUS
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PchLpcIoEnableDecodingSet (
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IN UINT16 LpcIoEnableDecoding
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);
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/**
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Set PCH eSPI CS1# IO enable decoding.
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Setup I/O Enables in DMI to the same value program in eSPI PCI offset A0h (eSPI CS1#).
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Note: Bit[15:10] of the source decode register is Read-Only. The IO range indicated by the Enables field
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in eSPI PCI offset A0h[13:10] is always forwarded by DMI to subtractive agent for handling.
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Please check EDS for detail of eSPI IO decode ranges bit definition.
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@param[in] IoEnableDecoding eSPI IO enable decoding bit settings.
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@retval EFI_SUCCESS Successfully completed.
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@retval EFI_UNSUPPORTED DMI configuration is locked
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**/
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EFI_STATUS
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PchEspiCs1IoEnableDecodingSet (
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IN UINT16 IoEnableDecoding
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);
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/**
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Set PCH IO port 80h cycle decoding to PCIE root port.
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System BIOS is likely to do this very soon after reset before PCI bus enumeration, it must ensure that
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the IO Base Address field (PCIe:1Ch[7:4]) contains a value greater than the IO Limit field (PCIe:1Ch[15:12])
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before setting the IOSE bit. Otherwise the bridge will positively decode IO range 000h - FFFh by its default
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IO range values.
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This cycle decoding is allowed to set when DMIC.SRL is 0.
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Programming steps:
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1. Program "RPR Destination ID", PCR[DMI] + 274Ch[31:16] to the Dest ID of RP.
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2. Program "Reserved Page Route", PCR[DMI] + 274Ch[11] to '1'. Use byte write on GCS+1 and leave the BILD bit which is RWO.
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3. Program IOSE bit of PCIE:Reg04h[0] to '1' for PCH to send such IO cycles to PCIe bus for subtractive decoding.
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@param[in] RpPhyNumber PCIE root port physical number.
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@retval EFI_SUCCESS Successfully completed.
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**/
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EFI_STATUS
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PchIoPort80DecodeSet (
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IN UINTN RpPhyNumber
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);
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/**
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Get IO APIC registers base address.
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@param[out] IoApicBase Buffer of IO APIC register address
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@retval EFI_SUCCESS Successfully completed.
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**/
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EFI_STATUS
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PchIoApicBaseGet (
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OUT UINT32 *IoApicBase
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);
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/**
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Get HPET base address.
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This function will be unavailable after P2SB is hidden by PSF.
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@param[out] HpetBase Buffer of HPET base address
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@retval EFI_SUCCESS Successfully completed.
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@retval EFI_INVALID_PARAMETER Invalid offset passed.
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**/
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EFI_STATUS
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PchHpetBaseGet (
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OUT UINT32 *HpetBase
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);
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#endif // _PCH_CYCLE_DECODING_LIB_H_
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