/** @file
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SSDT for FVP PCIe
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Copyright (c) 2017 - 2021, Arm Ltd. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "ArmPlatform.h"
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/*
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See ACPI 6.1 Section 6.2.13
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There are two ways that _PRT can be used.
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In the first model, a PCI Link device is used to provide additional
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configuration information such as whether the interrupt is Level or
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Edge triggered, it is active High or Low, Shared or Exclusive, etc.
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In the second model, the PCI interrupts are hardwired to specific
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interrupt inputs on the interrupt controller and are not
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configurable. In this case, the Source field in _PRT does not
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reference a device, but instead contains the value zero, and the
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Source Index field contains the global system interrupt to which the
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PCI interrupt is hardwired.
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We use the first model with link indirection to set the correct
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interrupt type as PCI defaults (Level Triggered, Active Low) are not
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compatible with GICv2.
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*/
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#define LNK_DEVICE(Unique_Id, Link_Name, irq) \
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Device (Link_Name) { \
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Name (_HID, EISAID("PNP0C0F")) \
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Name (_UID, Unique_Id) \
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Name (_PRS, ResourceTemplate() { \
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Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive) { irq } \
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}) \
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Method (_CRS, 0) { Return (_PRS) } \
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Method (_SRS, 1) { } \
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Method (_DIS) { } \
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}
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#define PRT_ENTRY(Address, Pin, Link) \
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Package (4) { \
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Address, /* uses the same format as _ADR */ \
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Pin, /* The PCI pin number of the device (0-INTA, 1-INTB, 2-INTC, 3-INTD) */ \
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Link, /* Interrupt allocated via Link device */ \
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Zero /* global system interrupt number (no used) */ \
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}
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/*
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See Reference [1] 6.1.1
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"High word Device #, Low word Function #. (for example, device 3,
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function 2 is 0x00030002). To refer to all the functions on a device #,
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use a function number of FFFF)."
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*/
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#define ROOT_PRT_ENTRY(Pin, Link) PRT_ENTRY (0x0000FFFF, Pin, Link) // Device 0 for Bridge.
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DefinitionBlock ("SsdtPci.aml", "SSDT", 2, "ARMLTD", "FVP-REVC", 1) {
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Scope(_SB) {
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//
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// PCI Root Complex
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//
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LNK_DEVICE (1, LNKA, 168)
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LNK_DEVICE (2, LNKB, 169)
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LNK_DEVICE (3, LNKC, 170)
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LNK_DEVICE (4, LNKD, 171)
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Device(PCI0)
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{
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Name (_HID, EISAID ("PNP0A08")) // PCI Express Root Bridge
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Name (_CID, EISAID ("PNP0A03")) // Compatible PCI Root Bridge
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Name (_SEG, Zero) // PCI Segment Group number
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Name (_BBN, Zero) // PCI Base Bus Number
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Name (_CCA, 1) // Initially mark the PCI coherent
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// Root Complex 0
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Device (RP0) {
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Name (_ADR, 0xF0000000) // Dev 0, Func 0
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}
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// PCI Routing Table
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Name (_PRT, Package () {
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ROOT_PRT_ENTRY (0, LNKA), // INTA
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ROOT_PRT_ENTRY (1, LNKB), // INTB
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ROOT_PRT_ENTRY (2, LNKC), // INTC
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ROOT_PRT_ENTRY (3, LNKD), // INTD
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})
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// Root complex resources
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Method (_CRS, 0, Serialized) {
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Name (RBUF, ResourceTemplate () {
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WordBusNumber ( // Bus numbers assigned to this root
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ResourceProducer,
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MinFixed, MaxFixed, PosDecode,
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0, // AddressGranularity
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0, // AddressMinimum - Minimum Bus Number
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255, // AddressMaximum - Maximum Bus Number
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0, // AddressTranslation - Set to 0
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256 // RangeLength - Number of Busses
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)
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DWordMemory ( // 32-bit BAR Windows
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ResourceProducer,
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PosDecode,
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MinFixed,
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MaxFixed,
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Cacheable,
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ReadWrite,
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0x00000000, // Granularity
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0x50000000, // Min Base Address
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0x57FFFFFF, // Max Base Address
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0x00000000, // Translate
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0x08000000 // Length
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)
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QWordMemory ( // 64-bit BAR Windows
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ResourceProducer,
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PosDecode,
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MinFixed,
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MaxFixed,
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Cacheable,
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ReadWrite,
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0x00000000, // Granularity
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0x4000000000, // Min Base Address
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0x40FFFFFFFF, // Max Base Address
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0x00000000, // Translate
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0x100000000 // Length
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)
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DWordIo ( // IO window
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ResourceProducer,
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MinFixed,
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MaxFixed,
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PosDecode,
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EntireRange,
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0x00000000, // Granularity
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0x00000000, // Min Base Address
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0x007fffff, // Max Base Address
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0x5f800000, // Translate
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0x00800000, // Length
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,
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,
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,
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TypeTranslation
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)
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}) // Name (RBUF)
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Return (RBUF)
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} // Method(_CRS)
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//
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// OS Control Handoff
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//
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Name (SUPP, Zero) // PCI _OSC Support Field value
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Name (CTRL, Zero) // PCI _OSC Control Field value
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/*
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See [1] 6.2.10, [2] 4.5
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*/
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Method (_OSC,4) {
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// Check for proper UUID
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If(LEqual (Arg0,ToUUID ("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
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// Create DWord-adressable fields from the Capabilities Buffer
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CreateDWordField (Arg3, 0, CDW1)
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CreateDWordField (Arg3, 4, CDW2)
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CreateDWordField (Arg3, 8, CDW3)
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// Save Capabilities DWord2 & 3
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Store (CDW2, SUPP)
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Store (CDW3, CTRL)
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// Only allow native hot plug control if OS supports:
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// * ASPM
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// * Clock PM
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// * MSI/MSI-X
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If(LNotEqual (And (SUPP, 0x16), 0x16)) {
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And (CTRL, 0x1E, CTRL) // Mask bit 0 (and undefined bits)
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}
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// Always allow native PME, AER (no dependencies)
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// Never allow SHPC (no SHPC controller in this system)
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And (CTRL, 0x1D, CTRL)
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If(LNotEqual (Arg1, One)) { // Unknown revision
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Or (CDW1, 0x08, CDW1)
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}
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If(LNotEqual (CDW3, CTRL)) { // Capabilities bits were masked
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Or (CDW1, 0x10, CDW1)
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}
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// Update DWORD3 in the buffer
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Store (CTRL,CDW3)
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Return (Arg3)
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} Else {
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Or (CDW1, 4, CDW1) // Unrecognized UUID
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Return (Arg3)
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}
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} // End _OSC
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} // PCI0
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}
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}
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