1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
| /** @file
| SSDT Serial Template
|
| Copyright (c) 2019 - 2020, Arm Limited. All rights reserved.<BR>
|
| SPDX-License-Identifier: BSD-2-Clause-Patent
|
| @par Reference(s):
| - Arm Server Base Boot Requirements (SBBR), s4.2.1.8 "SPCR".
|
| @par Glossary:
| - {template} - Data fixed up using AML Fixup APIs.
| **/
|
| DefinitionBlock ("SsdtSerialPortTemplate.aml", "SSDT", 2, "ARMLTD", "SERIAL", 1) {
| Scope (_SB) {
| // UART PL011
| Device (COM0) { // {template}
| Name (_UID, 0x0) // {template}
| Name (_HID, "HID0000") // {template}
| Name (_CID, "CID0000") // {template}
|
| Method(_STA) {
| Return(0xF)
| }
|
| Name (_CRS, ResourceTemplate() {
| QWordMemory (
| , // ResourceUsage
| , // Decode
| , // IsMinFixed
| , // IsMaxFixed
| , // Cacheable
| ReadWrite, // ReadAndWrite
| 0x0, // AddressGranularity
| 0xA0000000, // AddressMinimum // {template}
| 0xAFFFFFFF, // AddressMaximum // {template}
| 0, // AddressTranslation
| 0x10000000, // RangeLength // {template}
| , // ResourceSourceIndex
| , // ResourceSource
| , // DescriptorName
| , // MemoryRangeType
| // TranslationType
| ) // QWordMemory
| Interrupt (
| ResourceConsumer, // ResourceUsage
| Level, // EdgeLevel
| ActiveHigh, // ActiveLevel
| Exclusive, // Shared
| , // ResourceSourceIndex
| , // ResourceSource
| // DescriptorName
| ) {
| 0xA5 // {template}
| } // Interrupt
| }) // Name
| } // Device
| } // Scope (_SB)
| }
|
|
