/** @file
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*
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* Copyright (c) 2013-2017, ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*
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**/
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#ifndef GENERIC_WATCHDOG_H_
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#define GENERIC_WATCHDOG_H_
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// Refresh Frame:
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#define GENERIC_WDOG_REFRESH_REG ((UINTN)FixedPcdGet64 (PcdGenericWatchdogRefreshBase) + 0x000)
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// Control Frame:
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#define GENERIC_WDOG_CONTROL_STATUS_REG ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x000)
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#define GENERIC_WDOG_OFFSET_REG ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x008)
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#define GENERIC_WDOG_COMPARE_VALUE_REG_LOW ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x010)
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#define GENERIC_WDOG_COMPARE_VALUE_REG_HIGH ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x014)
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// Values of bit 0 of the Control/Status Register
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#define GENERIC_WDOG_ENABLED 1
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#define GENERIC_WDOG_DISABLED 0
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#endif // GENERIC_WATCHDOG_H_
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