RAMBOOT for MPC85xx Platforms
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==============================
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RAMBOOT literally means boot from DDR. But since DDR is volatile memory some
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pre-mechanism is required to load the DDR with the bootloader binary.
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- In case of SD and SPI boot this is done by BootROM code inside the chip
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itself.
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- In case of NAND boot FCM supports loading initial 4K code from NAND flash
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which can initialize the DDR and get the complete bootloader copied to DDR.
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In addition to the above there could be some more methods to initialize the DDR
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and load it manually.
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Two of them are described below.There is also an explanation as to where these
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methods could be handy.
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1. Load the RAM based bootloader onto DDR via JTAG/BDI interface. And then
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execute the bootloader from DDR.
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This may be handy in the following cases:
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- In very early stage of platform bringup where other boot options are not
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functional because of various reasons.
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- In case the support to program the flashes on the board is not available.
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2. Load the RAM based bootloader onto DDR using already existing bootloader on
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the board.And then execute the bootloader from DDR.
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Some usecases where this may be used:
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- While developing some new feature of u-boot, for example USB driver or
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SPI driver.
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Suppose the board already has a working bootloader on it. And you would
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prefer to keep it intact, at the same time want to test your bootloader.
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In this case you can get your test bootloader binary into DDR via tftp
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for example. Then execute the test bootloader.
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- Suppose a platform already has a propreitery bootloader which does not
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support for example AMP boot. In this case also RAM boot loader can be
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utilized.
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So basically when the original bootloader is required to be kept intact
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RAM based bootloader can offer an updated bootloader on the system.
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Both the above Bootloaders are slight variants of SDcard or SPI Flash
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bootloader or for that matter even NAND bootloader.
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All of them define CONFIG_SYS_RAMBOOT.
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The main difference among all of them is the way the pre-environment is getting
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configured and who is doing that.
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- In case of SD card and SPI flash bootloader this is done by On Chip BootROM inside the Si itself.
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- In case of NAND boot SPL/TPL code does it with some support from Si itself.
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- In case of the pure RAM based bootloaders we have to do it by JTAG manually or already existing bootloader.
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How to use them:
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1. Using JTAG
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Boot up in core hold off mode or stop the core after reset using JTAG
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interface.
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Preconfigure DDR/L2SRAM through JTAG interface.
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- setup DDR controller registers.
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- setup DDR LAWs
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- setup DDR TLB
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Load the RAM based boot loader to the proper location in DDR/L2SRAM.
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set up IAR (Instruction counter properly)
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Enable the core to execute.
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2. Using already existing bootloader.
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get the rambased boot loader binary into DDR/L2SRAM via tftp.
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execute the RAM based bootloader.
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=> tftp 11000000 u-boot-ram.bin
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=> go 1107f000
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Please note that L2SRAM can also be used instead of DDR if the SOC has
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sufficient size of L2SRAM.
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Necessary Code changes Required:
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=====================================
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Please note that below mentioned changes are for 85xx platforms.
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They have been tested on P1020/P2020/P1010 RDB.
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The main difference between the above two methods from technical perspective is
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that in 1st case SOC is just out of reset so it is in default configuration.
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(CCSRBAR is at 0xff700000).
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In the 2nd case bootloader has already re-located CCSRBAR to 0xffe00000
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1. File name-> boards.cfg
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There can be added specific Make options for RAMBoot. We can keep different
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options for the two cases mentioned above.
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for example
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P1020RDB_JTAG_RAMBOOT and P1020RDB_GO_RAMBOOT.
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2. platform config file
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for example include/configs/P1_P2_RDB.h
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#ifdef CONFIG_RAMBOOT
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#define CONFIG_SDCARD
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#endif
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This will finally use the CONFIG_SYS_RAMBOOT.
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3. Change CONFIG_SYS_CCSRBAR_DEFAULT in menuconfig accordingly.
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In the section of the particular SOC, for example P1020, pseudo code
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#if defined(CONFIG_GO)
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xffe00000
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#else
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#endif
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For JTAG RAMBOOT this is not required because CCSRBAR is at ff700000.
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