T1024 SoC Overview
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------------------
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The T1024/T1023 dual core and T1014/T1013 single core QorIQ communication processor
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combines two or one 64-bit Power Architecture e5500 core respectively with high
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performance datapath acceleration logic, and network peripheral bus interfaces
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required for networking and telecommunications. This processor can be used in
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applications such as enterprise WLAN access points, routers, switches, firewall
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and other packet processing intensive small enterprise and branch office appliances,
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and general-purpose embedded computing. Its high level of integration offers
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significant performance benefits and greatly helps to simplify board design.
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The T1024 SoC includes the following function and features:
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- two e5500 cores, each with a private 256 KB L2 cache
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- Up to 1.4 GHz with 64-bit ISA support (Power Architecture v2.06-compliant)
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- Three levels of instructions: User, supervisor, and hypervisor
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- Independent boot and reset
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- Secure boot capability
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- 256 KB shared L3 CoreNet platform cache (CPC)
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- Interconnect CoreNet platform
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- CoreNet coherency manager supporting coherent and noncoherent transactions
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with prioritization and bandwidth allocation amongst CoreNet endpoints
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- 150 Gbps coherent read bandwidth
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- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
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- Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions:
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- Packet parsing, classification, and distribution
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- Queue management for scheduling, packet sequencing, and congestion management
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- Cryptography Acceleration (SEC 5.x)
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- IEEE 1588 support
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- Hardware buffer management for buffer allocation and deallocation
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- MACSEC on DPAA-based Ethernet ports
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- Ethernet interfaces
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- Four 1 Gbps Ethernet controllers
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- Parallel Ethernet interfaces
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- Two RGMII interfaces
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- High speed peripheral interfaces
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- Three PCI Express 2.0 controllers/ports running at up to 5 GHz
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- One SATA controller supporting 1.5 and 3.0 Gb/s operation
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- One QSGMII interface
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- Four SGMII interface supporting 1000 Mbps
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- Three SGMII interfaces supporting up to 2500 Mbps
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- 10GbE XFI or 10Base-KR interface
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- Additional peripheral interfaces
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- Two USB 2.0 controllers with integrated PHY
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- SD/eSDHC/eMMC
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- eSPI controller
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- Four I2C controllers
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- Four UARTs
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- Four GPIO controllers
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- Integrated flash controller (IFC)
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- LCD interface (DIU) with 12 bit dual data rate
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- Multicore programmable interrupt controller (PIC)
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- Two 8-channel DMA engines
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- Single source clocking implementation
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- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
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- QUICC Engine block
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- 32-bit RISC controller for flexible support of the communications peripherals
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- Serial DMA channel for receive and transmit on all serial channels
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- Two universal communication controllers, supporting TDM, HDLC, and UART
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T1023 Personality
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------------------
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T1023 is a reduced personality of T1024 without QUICC Engine, DIU, and
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unavailable deep sleep. Rest of the blocks are almost same as T1024.
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Differences between T1024 and T1023
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Feature T1024 T1023
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QUICC Engine: yes no
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DIU: yes no
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Deep Sleep: yes no
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I2C controller: 4 3
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DDR: 64-bit 32-bit
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IFC: 32-bit 28-bit
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T1024QDS board Overview
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-----------------------
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- SERDES Connections
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4 lanes supporting the following:
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- PCI Express: supports Gen 1 and Gen 2
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- SGMII 1G and SGMII 2.5G
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- QSGMII
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- XFI
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- SATA 2.0
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- High-speed multiplexers route the SerDes traffic to appropriate slots or connectors.
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- Aurora debug with dedicated connectors.
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- DDR Controller
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- Supports up to 1600 MTPS data-rate.
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- Supports one DDR4 or DDR3L module using DDR4 to DDR3L adapter card.
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- Supports Single-, dual- or quad-rank DIMMs
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- DDR power supplies 1.35V (DDR3L)/1.20V (DDR4) to all devices with automatic tracking of VTT.
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- IFC/Local Bus
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- NAND Flash: 8-bit, async, up to 2GB
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- NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
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- NOR devices support 8 virtual banks
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- Socketed to allow alternate devices
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- GASIC: Simple (minimal) target within QIXIS FPGA
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- PromJET rapid memory download support
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- IFC Debug/Development card
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- Ethernet
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- Two on-board RGMII 10M/100M/1G ethernet ports.
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- One QSGMII interface
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- Four SGMII interface supporting 1Gbps
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- Three SGMII interfaces supporting 2.5Gbps
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- one 10Gbps XFI or 10Base-KR interface
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- QIXIS System Logic FPGA
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- Manages system power and reset sequencing.
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- Manages the configurations of DUT, board, and clock for dynamic shmoo.
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- Collects V-I-T data in background for code/power profiling.
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- Supports legacy TMT test features (POSt, IRS, SYSCLK-synchronous assertion).
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- General fault monitoring and logging.
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- Powered from ATX 'standby' power supply that allows continuous operation while rest of the system is off.
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- Clocks
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- System and DDR clock (SYSCLK, DDRCLK).
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- Switch selectable to one of 16 common settings in the interval of 64 MHz-166 MHz.
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- Software programmable in 1 MHz increments from 1-200 MHz.
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- SERDES clocks
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- Provides clocks to SerDes blocks and slots.
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- 100 MHz, 125 MHz and 156.25 MHz options.
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- Spread-spectrum option for 100 MHz.
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- Power Supplies
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- Dedicated PMBus regulator for VDD and VDDC.
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- Adjustable from 0.7V to 1.3V at 35A
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- VDD can be disabled independanty from VDDC for “deep sleep”.
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- DDR3L/DDR4 power supply for GVDD: 1.35 or 1.20V at up to 22A.
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- VTT/MVREF automatically track operating voltage.
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- Dedicated 2.5V VPP supply.
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- Dedicated regulators/filters for AVDD supplies.
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- Dedicated regulators for other supplies, for example OVDD, CVDD, DVDD, LVDD, POVDD, and EVDD.
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- Video
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- DIU supports video up to 1280x1024x32 bpp.
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- Chrontel CH7201 for HDMI connection.
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- TI DS90C387R for direct LCD connection.
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- Raw (not encoded) video connector for testing or other encoders.
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- USB
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- Supports two USB 2.0 ports with integrated PHYs.
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- Two type A ports with 5V@1.5A per port.
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- Second port can be converted to OTG mini-AB.
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- SDHC
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For T1024QDS, the SDHC port connects directly to an adapter card slot that has the following features:
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- upport for optional clock feedback paths.
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- Support for optional high-speed voltage translation direction controls.
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- Support for SD slots for: SD, SDHC (1x, 4x, 8x) and MMC.
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- Support for eMMC memory devices.
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- SPI
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-On-board support of 3 different devices and sizes.
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- Other IO
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- Two Serial ports
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- ProfiBus port
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- Four I2C ports
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Memory map on T1024QDS
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----------------------
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Start Address End Address Description Size
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0xF_FFDF_0000 0xF_FFDF_0FFF IFC - FPGA 4KB
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0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
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0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
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0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB
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0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB
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0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB
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0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
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0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
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0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
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0xF_E000_0000 0xF_E7FF_FFFF Promjet 128MB
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0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
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0xC_2000_0000 0xC_2FFF_FFFF PCI Express 3 Mem Space 256MB
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0xC_1000_0000 0xC_1FFF_FFFF PCI Express 2 Mem Space 256MB
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0xC_0000_0000 0xC_0FFF_FFFF PCI Express 1 Mem Space 256MB
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0x0_0000_0000 0x0_ffff_ffff DDR 4GB
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128MB NOR Flash memory Map
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--------------------------
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Start Address End Address Definition Max size
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0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB
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0xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB
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0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
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0xEFE00000 0xEFE3FFFF QE firmware (current bank) 256KB
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0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB
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0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB
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0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB
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0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
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0xEBF40000 0xEBFFFFFF U-Boot (alt bank) 768KB
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0xEBF20000 0xEBF3FFFF U-Boot env (alt bank) 128KB
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0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB
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0xEBE00000 0xEBE3FFFF QE firmware (alt bank) 256KB
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0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB
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0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB
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0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB
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0xE8000000 0xE801FFFF RCW (current bank) 128KB
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SerDes clock vs DIP-switch settings
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-----------------------------------
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SRDS_PRTCL_S1 SD1_REF_CLK1 SD1_REF_CLK2 SW4[1:4]
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0x6F 100MHz 125MHz 1101
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0xD6 100MHz 100MHz 1111
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0x99 156.25MHz 100MHz 1011
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T1024 Clock frequency
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----------------------
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BIN Core DDR Platform FMan
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Bin1: 1400MHz 1600MT/s 400MHz 700MHz
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Bin2: 1200MHz 1600MT/s 400MHz 600MHz
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Bin3: 1000MHz 1600MT/s 400MHz 500MHz
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Software configurations and board settings
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------------------------------------------
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1. NOR boot:
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a. build NOR boot image
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$ make T1024QDS_defconfig (For DDR3L, by default)
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or make T1024QDS_D4_defconfig (For DDR4)
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$ make
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b. program u-boot.bin image to NOR flash
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=> tftp 1000000 u-boot.bin
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=> pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
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set SW1[1:8] = '00010011', SW2[1] = '1', SW6[1:4] = '0000' for NOR boot
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Switching between default bank0 and alternate bank4 on NOR flash
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To change boot source to vbank4:
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via software: run command 'qixis_reset altbank' in U-Boot.
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via DIP-switch: set SW6[1:4] = '0100'
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To change boot source to vbank0:
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via software: run command 'qixis_reset' in U-Boot.
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via DIP-Switch: set SW6[1:4] = '0000'
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2. NAND Boot:
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a. build PBL image for NAND boot
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$ make T1024QDS_NAND_defconfig
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$ make
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b. program u-boot-with-spl-pbl.bin to NAND flash
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=> tftp 1000000 u-boot-with-spl-pbl.bin
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=> nand erase 0 $filesize
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=> nand write 1000000 0 $filesize
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set SW1[1:8] = '10000010', SW2[1] = '0' and SW6[1:4] = '1001' for NAND boot
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3. SPI Boot:
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a. build PBL image for SPI boot
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$ make T1024QDS_SPIFLASH_defconfig
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$ make
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b. program u-boot-with-spl-pbl.bin to SPI flash
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=> tftp 1000000 u-boot-with-spl-pbl.bin
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=> sf probe 0
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=> sf erase 0 f0000
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=> sf write 1000000 0 $filesize
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set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
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4. SD Boot:
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a. build PBL image for SD boot
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$ make T1024QDS_SDCARD_defconfig
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$ make
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b. program u-boot-with-spl-pbl.bin to SD/MMC card
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=> tftp 1000000 u-boot-with-spl-pbl.bin
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=> mmc write 1000000 8 0x800
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=> tftp 1000000 fsl_fman_ucode_t1024_xx.bin
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=> mmc write 1000000 0x820 80
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set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
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DIU/QE-TDM/SDXC settings
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-------------------
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a) For TDM Riser: set pin_mux=tdm in hwconfig
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b) For UCC(ProfiBus): set pin_mux=ucc in hwconfig
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c) For HDMI(DVI): set pin_mux=hdmi in hwconfig
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d) For LCD(DFP): set pin_mux=lcd in hwconfig
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e) For SDXC: set adaptor=sdxc in hwconfig
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2-stage NAND/SPI/SD boot loader
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-------------------------------
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PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM.
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SPL further initializes DDR using SPD and environment variables
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and copy U-Boot(768 KB) from NAND/SPI/SD device to DDR.
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Finally SPL transers control to U-Boot for futher booting.
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SPL has following features:
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- Executes within 256K
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- No relocation required
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Run time view of SPL framework
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-------------------------------------------------
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|Area | Address |
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-------------------------------------------------
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|SecureBoot header | 0xFFFC0000 (32KB) |
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-------------------------------------------------
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|GD, BD | 0xFFFC8000 (4KB) |
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-------------------------------------------------
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|ENV | 0xFFFC9000 (8KB) |
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-------------------------------------------------
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|HEAP | 0xFFFCB000 (30KB) |
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-------------------------------------------------
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|STACK | 0xFFFD8000 (22KB) |
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-------------------------------------------------
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|U-Boot SPL | 0xFFFD8000 (160KB) |
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-------------------------------------------------
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NAND Flash memory Map on T1024QDS
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-------------------------------------------------------------
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Start End Definition Size
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0x000000 0x0FFFFF U-Boot 1MB
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0x100000 0x15FFFF U-Boot env 8KB
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0x160000 0x17FFFF FMAN Ucode 128KB
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0x180000 0x19FFFF QE Firmware 128KB
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SD Card memory Map on T1024QDS
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----------------------------------------------------
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Block #blocks Definition Size
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0x008 2048 U-Boot img 1MB
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0x800 0016 U-Boot env 8KB
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0x820 0256 FMAN Ucode 128KB
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0x920 0256 QE Firmware 128KB
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SPI Flash memory Map on T1024QDS
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----------------------------------------------------
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Start End Definition Size
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0x000000 0x0FFFFF U-Boot img 1MB
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0x100000 0x101FFF U-Boot env 8KB
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0x110000 0x12FFFF FMAN Ucode 128KB
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0x130000 0x14FFFF QE Firmware 128KB
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For more details, please refer to T1024QDS Reference Manual and access
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website www.freescale.com and Freescale QorIQ SDK Infocenter document.
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