/*
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* (C) Copyright 2010
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* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __FSMC_NAND_H__
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#define __FSMC_NAND_H__
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#include <linux/mtd/rawnand.h>
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struct fsmc_regs {
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u32 ctrl; /* 0x00 */
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u8 reserved_1[0x40 - 0x04];
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u32 pc; /* 0x40 */
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u32 sts; /* 0x44 */
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u32 comm; /* 0x48 */
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u32 attrib; /* 0x4c */
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u32 ioata; /* 0x50 */
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u32 ecc1; /* 0x54 */
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u32 ecc2; /* 0x58 */
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u32 ecc3; /* 0x5c */
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u8 reserved_2[0xfe0 - 0x60];
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u32 peripid0; /* 0xfe0 */
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u32 peripid1; /* 0xfe4 */
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u32 peripid2; /* 0xfe8 */
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u32 peripid3; /* 0xfec */
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u32 pcellid0; /* 0xff0 */
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u32 pcellid1; /* 0xff4 */
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u32 pcellid2; /* 0xff8 */
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u32 pcellid3; /* 0xffc */
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};
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/* ctrl register definitions */
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#define FSMC_WP (1 << 7)
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/* pc register definitions */
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#define FSMC_RESET (1 << 0)
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#define FSMC_WAITON (1 << 1)
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#define FSMC_ENABLE (1 << 2)
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#define FSMC_DEVTYPE_NAND (1 << 3)
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#define FSMC_DEVWID_8 (0 << 4)
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#define FSMC_DEVWID_16 (1 << 4)
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#define FSMC_ECCEN (1 << 6)
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#define FSMC_ECCPLEN_512 (0 << 7)
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#define FSMC_ECCPLEN_256 (1 << 7)
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#define FSMC_TCLR_1 (1 << 9)
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#define FSMC_TAR_1 (1 << 13)
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/* sts register definitions */
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#define FSMC_CODE_RDY (1 << 15)
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/* comm register definitions */
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#define FSMC_TSET_0 (0 << 0)
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#define FSMC_TWAIT_6 (6 << 8)
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#define FSMC_THOLD_4 (4 << 16)
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#define FSMC_THIZ_1 (1 << 24)
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/* peripid2 register definitions */
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#define FSMC_REVISION_MSK (0xf)
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#define FSMC_REVISION_SHFT (0x4)
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#define FSMC_VER8 0x8
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/*
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* There are 13 bytes of ecc for every 512 byte block and it has to be read
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* consecutively and immediately after the 512 byte data block for hardware to
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* generate the error bit offsets
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* Managing the ecc bytes in the following way is easier. This way is similar to
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* oobfree structure maintained already in u-boot nand driver
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*/
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#define FSMC_MAX_ECCPLACE_ENTRIES 32
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struct fsmc_nand_eccplace {
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u32 offset;
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u32 length;
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};
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struct fsmc_eccplace {
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struct fsmc_nand_eccplace eccplace[FSMC_MAX_ECCPLACE_ENTRIES];
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};
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extern int fsmc_nand_init(struct nand_chip *nand);
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#endif
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