/* AArch64 Non-NEON ACLE intrinsics include file.
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Copyright (C) 2014-2020 Free Software Foundation, Inc.
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Contributed by ARM Ltd.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published
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by the Free Software Foundation; either version 3, or (at your
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option) any later version.
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GCC is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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Under Section 7 of GPL version 3, you are granted additional
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permissions described in the GCC Runtime Library Exception, version
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3.1, as published by the Free Software Foundation.
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You should have received a copy of the GNU General Public License and
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a copy of the GCC Runtime Library Exception along with this program;
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see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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<http://www.gnu.org/licenses/>. */
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#ifndef _GCC_ARM_ACLE_H
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#define _GCC_ARM_ACLE_H
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#pragma GCC push_options
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#pragma GCC target ("arch=armv8.3-a")
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__extension__ static __inline int32_t __attribute__ ((__always_inline__))
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__jcvt (double __a)
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{
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return __builtin_aarch64_jcvtzs (__a);
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}
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#pragma GCC pop_options
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#pragma GCC push_options
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#pragma GCC target ("arch=armv8.5-a")
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__extension__ static __inline float __attribute__ ((__always_inline__))
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__rint32zf (float __a)
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{
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return __builtin_aarch64_frint32zsf (__a);
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}
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__extension__ static __inline double __attribute__ ((__always_inline__))
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__rint32z (double __a)
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{
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return __builtin_aarch64_frint32zdf (__a);
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}
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__extension__ static __inline float __attribute__ ((__always_inline__))
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__rint64zf (float __a)
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{
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return __builtin_aarch64_frint64zsf (__a);
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}
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__extension__ static __inline double __attribute__ ((__always_inline__))
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__rint64z (double __a)
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{
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return __builtin_aarch64_frint64zdf (__a);
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}
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__extension__ static __inline float __attribute__ ((__always_inline__))
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__rint32xf (float __a)
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{
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return __builtin_aarch64_frint32xsf (__a);
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}
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__extension__ static __inline double __attribute__ ((__always_inline__))
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__rint32x (double __a)
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{
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return __builtin_aarch64_frint32xdf (__a);
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}
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__extension__ static __inline float __attribute__ ((__always_inline__))
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__rint64xf (float __a)
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{
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return __builtin_aarch64_frint64xsf (__a);
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}
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__extension__ static __inline double __attribute__ ((__always_inline__))
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__rint64x (double __a)
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{
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return __builtin_aarch64_frint64xdf (__a);
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}
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#pragma GCC pop_options
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#pragma GCC push_options
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#pragma GCC target ("+nothing+crc")
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__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
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__crc32b (uint32_t __a, uint8_t __b)
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{
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return __builtin_aarch64_crc32b (__a, __b);
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}
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__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
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__crc32cb (uint32_t __a, uint8_t __b)
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{
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return __builtin_aarch64_crc32cb (__a, __b);
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}
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__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
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__crc32ch (uint32_t __a, uint16_t __b)
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{
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return __builtin_aarch64_crc32ch (__a, __b);
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}
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__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
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__crc32cw (uint32_t __a, uint32_t __b)
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{
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return __builtin_aarch64_crc32cw (__a, __b);
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}
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__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
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__crc32cd (uint32_t __a, uint64_t __b)
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{
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return __builtin_aarch64_crc32cx (__a, __b);
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}
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__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
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__crc32h (uint32_t __a, uint16_t __b)
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{
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return __builtin_aarch64_crc32h (__a, __b);
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}
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__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
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__crc32w (uint32_t __a, uint32_t __b)
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{
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return __builtin_aarch64_crc32w (__a, __b);
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}
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__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
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__crc32d (uint32_t __a, uint64_t __b)
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{
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return __builtin_aarch64_crc32x (__a, __b);
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}
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#pragma GCC pop_options
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#ifdef __ARM_FEATURE_TME
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#pragma GCC push_options
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#pragma GCC target ("+nothing+tme")
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#define _TMFAILURE_REASON 0x00007fffu
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#define _TMFAILURE_RTRY 0x00008000u
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#define _TMFAILURE_CNCL 0x00010000u
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#define _TMFAILURE_MEM 0x00020000u
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#define _TMFAILURE_IMP 0x00040000u
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#define _TMFAILURE_ERR 0x00080000u
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#define _TMFAILURE_SIZE 0x00100000u
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#define _TMFAILURE_NEST 0x00200000u
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#define _TMFAILURE_DBG 0x00400000u
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#define _TMFAILURE_INT 0x00800000u
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#define _TMFAILURE_TRIVIAL 0x01000000u
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__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
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__tstart (void)
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{
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return __builtin_aarch64_tstart ();
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}
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__extension__ static __inline void __attribute__ ((__always_inline__))
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__tcommit (void)
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{
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__builtin_aarch64_tcommit ();
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}
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__extension__ static __inline void __attribute__ ((__always_inline__))
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__tcancel (const uint64_t __reason)
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{
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__builtin_aarch64_tcancel (__reason);
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}
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__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
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__ttest (void)
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{
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return __builtin_aarch64_ttest ();
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}
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#pragma GCC pop_options
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#endif
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#pragma GCC push_options
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#pragma GCC target ("+nothing+rng")
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__extension__ static __inline int __attribute__ ((__always_inline__))
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__rndr (uint64_t *__res)
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{
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return __builtin_aarch64_rndr (__res);
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}
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__extension__ static __inline int __attribute__ ((__always_inline__))
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__rndrrs (uint64_t *__res)
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{
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return __builtin_aarch64_rndrrs (__res);
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}
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#pragma GCC pop_options
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#pragma GCC push_options
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#pragma GCC target ("arch=armv8.5-a+memtag")
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#define __arm_mte_create_random_tag(__ptr, __u64_mask) \
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__builtin_aarch64_memtag_irg(__ptr, __u64_mask)
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#define __arm_mte_exclude_tag(__ptr, __u64_excluded) \
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__builtin_aarch64_memtag_gmi(__ptr, __u64_excluded)
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#define __arm_mte_ptrdiff(__ptr_a, __ptr_b) \
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__builtin_aarch64_memtag_subp(__ptr_a, __ptr_b)
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#define __arm_mte_increment_tag(__ptr, __u_offset) \
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__builtin_aarch64_memtag_inc_tag(__ptr, __u_offset)
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#define __arm_mte_set_tag(__tagged_address) \
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__builtin_aarch64_memtag_set_tag(__tagged_address)
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#define __arm_mte_get_tag(__address) \
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__builtin_aarch64_memtag_get_tag(__address)
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#pragma GCC pop_options
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#ifdef __cplusplus
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}
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#endif
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#endif
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