/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Defining registers address and its bit definitions of MAX96745
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*
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* Copyright (c) 2022 Rockchip Electronics Co. Ltd.
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*/
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#ifndef _MFD_MAX96745_H_
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#define _MFD_MAX96745_H_
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#include <linux/bitfield.h>
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struct max96745 {
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struct device *dev;
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struct regmap *regmap;
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struct i2c_mux_core *muxc;
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struct gpio_desc *enable_gpio;
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struct gpio_desc *pwdnb_gpio;
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struct extcon_dev *extcon;
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bool idle_disc;
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};
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#define GPIO_A_REG(gpio) (0x0200 + ((gpio) * 8))
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#define GPIO_B_REG(gpio) (0x0201 + ((gpio) * 8))
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#define GPIO_C_REG(gpio) (0x0202 + ((gpio) * 8))
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#define GPIO_D_REG(gpio) (0x0203 + ((gpio) * 8))
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/* 0005h */
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#define PU_LF3 BIT(3)
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#define PU_LF2 BIT(2)
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#define PU_LF1 BIT(1)
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#define PU_LF0 BIT(0)
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/* 0010h */
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#define RESET_ALL BIT(7)
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#define SLEEP BIT(3)
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/* 0011h */
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#define CXTP_B BIT(2)
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#define CXTP_A BIT(0)
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/* 0013h */
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#define LOCKED BIT(3)
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#define ERROR BIT(2)
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/* 0026h */
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#define LF_0 GENMASK(2, 0)
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#define LF_1 GENMASK(6, 4)
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/* 0027h */
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#define LF_2 GENMASK(2, 0)
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#define LF_3 GENMASK(6, 4)
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/* 0028h, 0032h */
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#define LINK_EN BIT(7)
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#define TX_RATE GENMASK(3, 2)
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/* 0029h, 0033h */
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#define RESET_LINK BIT(0)
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#define RESET_ONESHOT BIT(1)
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/* 002Ah, 0034h */
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#define LINK_LOCKED BIT(0)
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/* 0076h, 0086h */
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#define DIS_REM_CC BIT(7)
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/* 0100h */
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#define VID_LINK_SEL GENMASK(2, 1)
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#define VID_TX_EN BIT(0)
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/* 0101h */
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#define BPP GENMASK(5, 0)
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/* 0102h */
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#define PCLKDET_A BIT(7)
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#define DRIFT_ERR_A BIT(6)
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#define OVERFLOW_A BIT(5)
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#define FIFO_WARN_A BIT(4)
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#define LIM_HEART BIT(2)
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/* 0107h */
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#define VID_TX_ACTIVE_B BIT(7)
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#define VID_TX_ACTIVE_A BIT(6)
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/* 0108h */
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#define PCLKDET_B BIT(7)
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#define DRIFT_ERR_B BIT(6)
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#define OVERFLOW_B BIT(5)
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#define FIFO_WARN_B BIT(4)
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/* 0200h */
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#define RES_CFG BIT(7)
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#define TX_COM_EN BIT(5)
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#define GPIO_OUT BIT(4)
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#define GPIO_IN BIT(3)
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#define GPIO_OUT_DIS BIT(0)
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/* 0201h */
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#define PULL_UPDN_SEL GENMASK(7, 6)
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#define OUT_TYPEC BIT(5)
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#define GPIO_TX_ID GENMASK(4, 0)
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/* 0202h */
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#define OVR_RES_CFG BIT(7)
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#define IO_EDGE_RATE GENMASK(6, 5)
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#define GPIO_RX_ID GENMASK(4, 0)
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/* 0203h */
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#define GPIO_IO_RX_EN BIT(5)
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#define GPIO_OUT_LGC BIT(4)
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#define GPIO_RX_EN_B BIT(3)
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#define GPIO_TX_EN_B BIT(2)
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#define GPIO_RX_EN_A BIT(1)
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#define GPIO_TX_EN_A BIT(0)
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/* 0750h */
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#define FRCZEROPAD GENMASK(7, 6)
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#define FRCZPEN BIT(5)
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#define FRCSDGAIN BIT(4)
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#define FRCSDEN BIT(3)
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#define FRCGAIN GENMASK(2, 1)
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#define FRCEN BIT(0)
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/* 0751h */
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#define FRCDATAWIDTH BIT(3)
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#define FRCASYNCEN BIT(2)
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#define FRCHSPOL BIT(1)
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#define FRCVSPOL BIT(0)
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/* 0752h */
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#define FRCDCMODE GENMASK(1, 0)
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/* 641Ah */
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#define DPRX_TRAIN_STATE GENMASK(7, 4)
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/* 7000h */
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#define LINK_ENABLE BIT(0)
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/* 7070h */
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#define MAX_LANE_COUNT GENMASK(7, 0)
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/* 7074h */
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#define MAX_LINK_RATE GENMASK(7, 0)
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#endif /* _MFD_MAX96745_H_ */
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