/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. */
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#ifndef __ABI_MACH_T194_CLOCK_H
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#define __ABI_MACH_T194_CLOCK_H
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#define TEGRA194_CLK_ACTMON 1
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#define TEGRA194_CLK_ADSP 2
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#define TEGRA194_CLK_ADSPNEON 3
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#define TEGRA194_CLK_AHUB 4
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#define TEGRA194_CLK_APB2APE 5
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#define TEGRA194_CLK_APE 6
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#define TEGRA194_CLK_AUD_MCLK 7
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#define TEGRA194_CLK_AXI_CBB 8
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#define TEGRA194_CLK_CAN1 9
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#define TEGRA194_CLK_CAN1_HOST 10
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#define TEGRA194_CLK_CAN2 11
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#define TEGRA194_CLK_CAN2_HOST 12
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#define TEGRA194_CLK_CEC 13
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#define TEGRA194_CLK_CLK_M 14
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#define TEGRA194_CLK_DMIC1 15
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#define TEGRA194_CLK_DMIC2 16
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#define TEGRA194_CLK_DMIC3 17
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#define TEGRA194_CLK_DMIC4 18
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#define TEGRA194_CLK_DPAUX 19
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#define TEGRA194_CLK_DPAUX1 20
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#define TEGRA194_CLK_ACLK 21
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#define TEGRA194_CLK_MSS_ENCRYPT 22
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#define TEGRA194_CLK_EQOS_RX_INPUT 23
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#define TEGRA194_CLK_IQC2 24
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#define TEGRA194_CLK_AON_APB 25
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#define TEGRA194_CLK_AON_NIC 26
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#define TEGRA194_CLK_AON_CPU_NIC 27
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#define TEGRA194_CLK_PLLA1 28
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#define TEGRA194_CLK_DSPK1 29
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#define TEGRA194_CLK_DSPK2 30
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#define TEGRA194_CLK_EMC 31
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#define TEGRA194_CLK_EQOS_AXI 32
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#define TEGRA194_CLK_EQOS_PTP_REF 33
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#define TEGRA194_CLK_EQOS_RX 34
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#define TEGRA194_CLK_EQOS_TX 35
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#define TEGRA194_CLK_EXTPERIPH1 36
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#define TEGRA194_CLK_EXTPERIPH2 37
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#define TEGRA194_CLK_EXTPERIPH3 38
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#define TEGRA194_CLK_EXTPERIPH4 39
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#define TEGRA194_CLK_FUSE 40
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#define TEGRA194_CLK_GPCCLK 41
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#define TEGRA194_CLK_GPU_PWR 42
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#define TEGRA194_CLK_HDA 43
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#define TEGRA194_CLK_HDA2CODEC_2X 44
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#define TEGRA194_CLK_HDA2HDMICODEC 45
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#define TEGRA194_CLK_HOST1X 46
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#define TEGRA194_CLK_HSIC_TRK 47
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#define TEGRA194_CLK_I2C1 48
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#define TEGRA194_CLK_I2C2 49
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#define TEGRA194_CLK_I2C3 50
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#define TEGRA194_CLK_I2C4 51
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#define TEGRA194_CLK_I2C6 52
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#define TEGRA194_CLK_I2C7 53
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#define TEGRA194_CLK_I2C8 54
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#define TEGRA194_CLK_I2C9 55
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#define TEGRA194_CLK_I2S1 56
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#define TEGRA194_CLK_I2S1_SYNC_INPUT 57
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#define TEGRA194_CLK_I2S2 58
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#define TEGRA194_CLK_I2S2_SYNC_INPUT 59
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#define TEGRA194_CLK_I2S3 60
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#define TEGRA194_CLK_I2S3_SYNC_INPUT 61
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#define TEGRA194_CLK_I2S4 62
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#define TEGRA194_CLK_I2S4_SYNC_INPUT 63
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#define TEGRA194_CLK_I2S5 64
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#define TEGRA194_CLK_I2S5_SYNC_INPUT 65
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#define TEGRA194_CLK_I2S6 66
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#define TEGRA194_CLK_I2S6_SYNC_INPUT 67
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#define TEGRA194_CLK_IQC1 68
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#define TEGRA194_CLK_ISP 69
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#define TEGRA194_CLK_KFUSE 70
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#define TEGRA194_CLK_MAUD 71
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#define TEGRA194_CLK_MIPI_CAL 72
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#define TEGRA194_CLK_MPHY_CORE_PLL_FIXED 73
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#define TEGRA194_CLK_MPHY_L0_RX_ANA 74
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#define TEGRA194_CLK_MPHY_L0_RX_LS_BIT 75
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#define TEGRA194_CLK_MPHY_L0_RX_SYMB 76
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#define TEGRA194_CLK_MPHY_L0_TX_LS_3XBIT 77
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#define TEGRA194_CLK_MPHY_L0_TX_SYMB 78
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#define TEGRA194_CLK_MPHY_L1_RX_ANA 79
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#define TEGRA194_CLK_MPHY_TX_1MHZ_REF 80
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#define TEGRA194_CLK_NVCSI 81
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#define TEGRA194_CLK_NVCSILP 82
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#define TEGRA194_CLK_NVDEC 83
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#define TEGRA194_CLK_NVDISPLAYHUB 84
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#define TEGRA194_CLK_NVDISPLAY_DISP 85
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#define TEGRA194_CLK_NVDISPLAY_P0 86
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#define TEGRA194_CLK_NVDISPLAY_P1 87
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#define TEGRA194_CLK_NVDISPLAY_P2 88
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#define TEGRA194_CLK_NVENC 89
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#define TEGRA194_CLK_NVJPG 90
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#define TEGRA194_CLK_OSC 91
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#define TEGRA194_CLK_AON_TOUCH 92
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#define TEGRA194_CLK_PLLA 93
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#define TEGRA194_CLK_PLLAON 94
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#define TEGRA194_CLK_PLLD 95
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#define TEGRA194_CLK_PLLD2 96
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#define TEGRA194_CLK_PLLD3 97
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#define TEGRA194_CLK_PLLDP 98
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#define TEGRA194_CLK_PLLD4 99
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#define TEGRA194_CLK_PLLE 100
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#define TEGRA194_CLK_PLLP 101
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#define TEGRA194_CLK_PLLP_OUT0 102
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#define TEGRA194_CLK_UTMIPLL 103
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#define TEGRA194_CLK_PLLA_OUT0 104
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#define TEGRA194_CLK_PWM1 105
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#define TEGRA194_CLK_PWM2 106
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#define TEGRA194_CLK_PWM3 107
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#define TEGRA194_CLK_PWM4 108
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#define TEGRA194_CLK_PWM5 109
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#define TEGRA194_CLK_PWM6 110
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#define TEGRA194_CLK_PWM7 111
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#define TEGRA194_CLK_PWM8 112
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#define TEGRA194_CLK_RCE_CPU_NIC 113
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#define TEGRA194_CLK_RCE_NIC 114
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#define TEGRA194_CLK_SATA 115
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#define TEGRA194_CLK_SATA_OOB 116
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#define TEGRA194_CLK_AON_I2C_SLOW 117
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#define TEGRA194_CLK_SCE_CPU_NIC 118
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#define TEGRA194_CLK_SCE_NIC 119
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#define TEGRA194_CLK_SDMMC1 120
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#define TEGRA194_CLK_UPHY_PLL3 121
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#define TEGRA194_CLK_SDMMC3 122
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#define TEGRA194_CLK_SDMMC4 123
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#define TEGRA194_CLK_SE 124
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#define TEGRA194_CLK_SOR0_OUT 125
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#define TEGRA194_CLK_SOR0_REF 126
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#define TEGRA194_CLK_SOR0_PAD_CLKOUT 127
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#define TEGRA194_CLK_SOR1_OUT 128
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#define TEGRA194_CLK_SOR1_REF 129
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#define TEGRA194_CLK_SOR1_PAD_CLKOUT 130
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#define TEGRA194_CLK_SOR_SAFE 131
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#define TEGRA194_CLK_IQC1_IN 132
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#define TEGRA194_CLK_IQC2_IN 133
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#define TEGRA194_CLK_DMIC5 134
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#define TEGRA194_CLK_SPI1 135
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#define TEGRA194_CLK_SPI2 136
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#define TEGRA194_CLK_SPI3 137
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#define TEGRA194_CLK_I2C_SLOW 138
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#define TEGRA194_CLK_SYNC_DMIC1 139
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#define TEGRA194_CLK_SYNC_DMIC2 140
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#define TEGRA194_CLK_SYNC_DMIC3 141
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#define TEGRA194_CLK_SYNC_DMIC4 142
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#define TEGRA194_CLK_SYNC_DSPK1 143
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#define TEGRA194_CLK_SYNC_DSPK2 144
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#define TEGRA194_CLK_SYNC_I2S1 145
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#define TEGRA194_CLK_SYNC_I2S2 146
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#define TEGRA194_CLK_SYNC_I2S3 147
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#define TEGRA194_CLK_SYNC_I2S4 148
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#define TEGRA194_CLK_SYNC_I2S5 149
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#define TEGRA194_CLK_SYNC_I2S6 150
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#define TEGRA194_CLK_MPHY_FORCE_LS_MODE 151
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#define TEGRA194_CLK_TACH 152
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#define TEGRA194_CLK_TSEC 153
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#define TEGRA194_CLK_TSECB 154
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#define TEGRA194_CLK_UARTA 155
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#define TEGRA194_CLK_UARTB 156
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#define TEGRA194_CLK_UARTC 157
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#define TEGRA194_CLK_UARTD 158
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#define TEGRA194_CLK_UARTE 159
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#define TEGRA194_CLK_UARTF 160
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#define TEGRA194_CLK_UARTG 161
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#define TEGRA194_CLK_UART_FST_MIPI_CAL 162
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#define TEGRA194_CLK_UFSDEV_REF 163
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#define TEGRA194_CLK_UFSHC 164
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#define TEGRA194_CLK_USB2_TRK 165
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#define TEGRA194_CLK_VI 166
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#define TEGRA194_CLK_VIC 167
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#define TEGRA194_CLK_PVA0_AXI 168
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#define TEGRA194_CLK_PVA0_VPS0 169
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#define TEGRA194_CLK_PVA0_VPS1 170
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#define TEGRA194_CLK_PVA1_AXI 171
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#define TEGRA194_CLK_PVA1_VPS0 172
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#define TEGRA194_CLK_PVA1_VPS1 173
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#define TEGRA194_CLK_DLA0_FALCON 174
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#define TEGRA194_CLK_DLA0_CORE 175
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#define TEGRA194_CLK_DLA1_FALCON 176
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#define TEGRA194_CLK_DLA1_CORE 177
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#define TEGRA194_CLK_SOR2_OUT 178
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#define TEGRA194_CLK_SOR2_REF 179
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#define TEGRA194_CLK_SOR2_PAD_CLKOUT 180
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#define TEGRA194_CLK_SOR3_OUT 181
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#define TEGRA194_CLK_SOR3_REF 182
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#define TEGRA194_CLK_SOR3_PAD_CLKOUT 183
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#define TEGRA194_CLK_NVDISPLAY_P3 184
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#define TEGRA194_CLK_DPAUX2 185
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#define TEGRA194_CLK_DPAUX3 186
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#define TEGRA194_CLK_NVDEC1 187
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#define TEGRA194_CLK_NVENC1 188
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#define TEGRA194_CLK_SE_FREE 189
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#define TEGRA194_CLK_UARTH 190
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#define TEGRA194_CLK_FUSE_SERIAL 191
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#define TEGRA194_CLK_QSPI0 192
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#define TEGRA194_CLK_QSPI1 193
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#define TEGRA194_CLK_QSPI0_PM 194
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#define TEGRA194_CLK_QSPI1_PM 195
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#define TEGRA194_CLK_VI_CONST 196
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#define TEGRA194_CLK_NAFLL_BPMP 197
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#define TEGRA194_CLK_NAFLL_SCE 198
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#define TEGRA194_CLK_NAFLL_NVDEC 199
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#define TEGRA194_CLK_NAFLL_NVJPG 200
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#define TEGRA194_CLK_NAFLL_TSEC 201
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#define TEGRA194_CLK_NAFLL_TSECB 202
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#define TEGRA194_CLK_NAFLL_VI 203
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#define TEGRA194_CLK_NAFLL_SE 204
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#define TEGRA194_CLK_NAFLL_NVENC 205
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#define TEGRA194_CLK_NAFLL_ISP 206
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#define TEGRA194_CLK_NAFLL_VIC 207
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#define TEGRA194_CLK_NAFLL_NVDISPLAYHUB 208
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#define TEGRA194_CLK_NAFLL_AXICBB 209
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#define TEGRA194_CLK_NAFLL_DLA 210
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#define TEGRA194_CLK_NAFLL_PVA_CORE 211
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#define TEGRA194_CLK_NAFLL_PVA_VPS 212
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#define TEGRA194_CLK_NAFLL_CVNAS 213
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#define TEGRA194_CLK_NAFLL_RCE 214
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#define TEGRA194_CLK_NAFLL_NVENC1 215
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#define TEGRA194_CLK_NAFLL_DLA_FALCON 216
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#define TEGRA194_CLK_NAFLL_NVDEC1 217
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#define TEGRA194_CLK_NAFLL_GPU 218
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#define TEGRA194_CLK_SDMMC_LEGACY_TM 219
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#define TEGRA194_CLK_PEX0_CORE_0 220
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#define TEGRA194_CLK_PEX0_CORE_1 221
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#define TEGRA194_CLK_PEX0_CORE_2 222
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#define TEGRA194_CLK_PEX0_CORE_3 223
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#define TEGRA194_CLK_PEX0_CORE_4 224
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#define TEGRA194_CLK_PEX1_CORE_5 225
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#define TEGRA194_CLK_PEX_REF1 226
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#define TEGRA194_CLK_PEX_REF2 227
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#define TEGRA194_CLK_CSI_A 229
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#define TEGRA194_CLK_CSI_B 230
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#define TEGRA194_CLK_CSI_C 231
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#define TEGRA194_CLK_CSI_D 232
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#define TEGRA194_CLK_CSI_E 233
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#define TEGRA194_CLK_CSI_F 234
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#define TEGRA194_CLK_CSI_G 235
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#define TEGRA194_CLK_CSI_H 236
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#define TEGRA194_CLK_PLLC4 237
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#define TEGRA194_CLK_PLLC4_OUT 238
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#define TEGRA194_CLK_PLLC4_OUT1 239
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#define TEGRA194_CLK_PLLC4_OUT2 240
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#define TEGRA194_CLK_PLLC4_MUXED 241
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#define TEGRA194_CLK_PLLC4_VCO_DIV2 242
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#define TEGRA194_CLK_CSI_A_PAD 244
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#define TEGRA194_CLK_CSI_B_PAD 245
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#define TEGRA194_CLK_CSI_C_PAD 246
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#define TEGRA194_CLK_CSI_D_PAD 247
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#define TEGRA194_CLK_CSI_E_PAD 248
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#define TEGRA194_CLK_CSI_F_PAD 249
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#define TEGRA194_CLK_CSI_G_PAD 250
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#define TEGRA194_CLK_CSI_H_PAD 251
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#define TEGRA194_CLK_PEX_SATA_USB_RX_BYP 254
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#define TEGRA194_CLK_PEX_USB_PAD_PLL0_MGMT 255
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#define TEGRA194_CLK_PEX_USB_PAD_PLL1_MGMT 256
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#define TEGRA194_CLK_PEX_USB_PAD_PLL2_MGMT 257
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#define TEGRA194_CLK_PEX_USB_PAD_PLL3_MGMT 258
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#define TEGRA194_CLK_XUSB_CORE_DEV 265
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#define TEGRA194_CLK_XUSB_CORE_MUX 266
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#define TEGRA194_CLK_XUSB_CORE_HOST 267
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#define TEGRA194_CLK_XUSB_CORE_SS 268
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#define TEGRA194_CLK_XUSB_FALCON 269
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#define TEGRA194_CLK_XUSB_FALCON_HOST 270
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#define TEGRA194_CLK_XUSB_FALCON_SS 271
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#define TEGRA194_CLK_XUSB_FS 272
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#define TEGRA194_CLK_XUSB_FS_HOST 273
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#define TEGRA194_CLK_XUSB_FS_DEV 274
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#define TEGRA194_CLK_XUSB_SS 275
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#define TEGRA194_CLK_XUSB_SS_DEV 276
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#define TEGRA194_CLK_XUSB_SS_SUPERSPEED 277
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#define TEGRA194_CLK_PLLDISPHUB 278
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#define TEGRA194_CLK_PLLDISPHUB_DIV 279
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#define TEGRA194_CLK_NAFLL_CLUSTER0 280
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#define TEGRA194_CLK_NAFLL_CLUSTER1 281
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#define TEGRA194_CLK_NAFLL_CLUSTER2 282
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#define TEGRA194_CLK_NAFLL_CLUSTER3 283
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#define TEGRA194_CLK_CAN1_CORE 284
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#define TEGRA194_CLK_CAN2_CORE 285
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#define TEGRA194_CLK_PLLA1_OUT1 286
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#define TEGRA194_CLK_PLLREFE_VCOOUT 288
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#define TEGRA194_CLK_CLK_32K 289
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#define TEGRA194_CLK_SPDIFIN_SYNC_INPUT 290
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#define TEGRA194_CLK_UTMIPLL_CLKOUT48 291
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#define TEGRA194_CLK_UTMIPLL_CLKOUT480 292
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#define TEGRA194_CLK_CVNAS 293
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#define TEGRA194_CLK_PLLNVCSI 294
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#define TEGRA194_CLK_PVA0_CPU_AXI 295
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#define TEGRA194_CLK_PVA1_CPU_AXI 296
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#define TEGRA194_CLK_PVA0_VPS 297
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#define TEGRA194_CLK_PVA1_VPS 298
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#define TEGRA194_CLK_DLA0_FALCON_MUX 299
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#define TEGRA194_CLK_DLA1_FALCON_MUX 300
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#define TEGRA194_CLK_DLA0_CORE_MUX 301
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#define TEGRA194_CLK_DLA1_CORE_MUX 302
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#define TEGRA194_CLK_UTMIPLL_HPS 304
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#define TEGRA194_CLK_I2C5 305
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#define TEGRA194_CLK_I2C10 306
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#define TEGRA194_CLK_BPMP_CPU_NIC 307
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#define TEGRA194_CLK_BPMP_APB 308
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#define TEGRA194_CLK_TSC 309
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#define TEGRA194_CLK_EMCSA 310
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#define TEGRA194_CLK_EMCSB 311
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#define TEGRA194_CLK_EMCSC 312
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#define TEGRA194_CLK_EMCSD 313
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#define TEGRA194_CLK_PLLC 314
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#define TEGRA194_CLK_PLLC2 315
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#define TEGRA194_CLK_PLLC3 316
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#define TEGRA194_CLK_TSC_REF 317
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#define TEGRA194_CLK_FUSE_BURN 318
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#define TEGRA194_CLK_PEX0_CORE_0M 319
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#define TEGRA194_CLK_PEX0_CORE_1M 320
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#define TEGRA194_CLK_PEX0_CORE_2M 321
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#define TEGRA194_CLK_PEX0_CORE_3M 322
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#define TEGRA194_CLK_PEX0_CORE_4M 323
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#define TEGRA194_CLK_PEX1_CORE_5M 324
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#define TEGRA194_CLK_PLLE_HPS 326
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#endif
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