/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2013 Samsung Electronics Co., Ltd.
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* Author: Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
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*
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* Device Tree binding constants for Samsung S5PV210 clock controller.
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*/
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#ifndef _DT_BINDINGS_CLOCK_S5PV210_H
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#define _DT_BINDINGS_CLOCK_S5PV210_H
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/* Core clocks. */
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#define FIN_PLL 1
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#define FOUT_APLL 2
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#define FOUT_MPLL 3
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#define FOUT_EPLL 4
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#define FOUT_VPLL 5
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/* Muxes. */
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#define MOUT_FLASH 6
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#define MOUT_PSYS 7
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#define MOUT_DSYS 8
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#define MOUT_MSYS 9
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#define MOUT_VPLL 10
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#define MOUT_EPLL 11
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#define MOUT_MPLL 12
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#define MOUT_APLL 13
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#define MOUT_VPLLSRC 14
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#define MOUT_CSIS 15
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#define MOUT_FIMD 16
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#define MOUT_CAM1 17
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#define MOUT_CAM0 18
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#define MOUT_DAC 19
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#define MOUT_MIXER 20
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#define MOUT_HDMI 21
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#define MOUT_G2D 22
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#define MOUT_MFC 23
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#define MOUT_G3D 24
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#define MOUT_FIMC2 25
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#define MOUT_FIMC1 26
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#define MOUT_FIMC0 27
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#define MOUT_UART3 28
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#define MOUT_UART2 29
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#define MOUT_UART1 30
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#define MOUT_UART0 31
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#define MOUT_MMC3 32
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#define MOUT_MMC2 33
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#define MOUT_MMC1 34
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#define MOUT_MMC0 35
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#define MOUT_PWM 36
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#define MOUT_SPI0 37
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#define MOUT_SPI1 38
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#define MOUT_DMC0 39
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#define MOUT_PWI 40
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#define MOUT_HPM 41
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#define MOUT_SPDIF 42
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#define MOUT_AUDIO2 43
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#define MOUT_AUDIO1 44
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#define MOUT_AUDIO0 45
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/* Dividers. */
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#define DOUT_PCLKP 46
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#define DOUT_HCLKP 47
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#define DOUT_PCLKD 48
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#define DOUT_HCLKD 49
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#define DOUT_PCLKM 50
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#define DOUT_HCLKM 51
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#define DOUT_A2M 52
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#define DOUT_APLL 53
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#define DOUT_CSIS 54
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#define DOUT_FIMD 55
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#define DOUT_CAM1 56
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#define DOUT_CAM0 57
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#define DOUT_TBLK 58
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#define DOUT_G2D 59
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#define DOUT_MFC 60
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#define DOUT_G3D 61
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#define DOUT_FIMC2 62
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#define DOUT_FIMC1 63
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#define DOUT_FIMC0 64
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#define DOUT_UART3 65
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#define DOUT_UART2 66
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#define DOUT_UART1 67
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#define DOUT_UART0 68
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#define DOUT_MMC3 69
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#define DOUT_MMC2 70
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#define DOUT_MMC1 71
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#define DOUT_MMC0 72
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#define DOUT_PWM 73
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#define DOUT_SPI1 74
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#define DOUT_SPI0 75
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#define DOUT_DMC0 76
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#define DOUT_PWI 77
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#define DOUT_HPM 78
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#define DOUT_COPY 79
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#define DOUT_FLASH 80
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#define DOUT_AUDIO2 81
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#define DOUT_AUDIO1 82
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#define DOUT_AUDIO0 83
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#define DOUT_DPM 84
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#define DOUT_DVSEM 85
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/* Gates */
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#define SCLK_FIMC 86
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#define CLK_CSIS 87
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#define CLK_ROTATOR 88
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#define CLK_FIMC2 89
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#define CLK_FIMC1 90
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#define CLK_FIMC0 91
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#define CLK_MFC 92
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#define CLK_G2D 93
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#define CLK_G3D 94
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#define CLK_IMEM 95
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#define CLK_PDMA1 96
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#define CLK_PDMA0 97
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#define CLK_MDMA 98
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#define CLK_DMC1 99
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#define CLK_DMC0 100
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#define CLK_NFCON 101
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#define CLK_SROMC 102
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#define CLK_CFCON 103
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#define CLK_NANDXL 104
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#define CLK_USB_HOST 105
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#define CLK_USB_OTG 106
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#define CLK_HDMI 107
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#define CLK_TVENC 108
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#define CLK_MIXER 109
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#define CLK_VP 110
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#define CLK_DSIM 111
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#define CLK_FIMD 112
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#define CLK_TZIC3 113
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#define CLK_TZIC2 114
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#define CLK_TZIC1 115
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#define CLK_TZIC0 116
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#define CLK_VIC3 117
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#define CLK_VIC2 118
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#define CLK_VIC1 119
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#define CLK_VIC0 120
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#define CLK_TSI 121
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#define CLK_HSMMC3 122
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#define CLK_HSMMC2 123
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#define CLK_HSMMC1 124
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#define CLK_HSMMC0 125
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#define CLK_JTAG 126
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#define CLK_MODEMIF 127
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#define CLK_CORESIGHT 128
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#define CLK_SDM 129
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#define CLK_SECSS 130
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#define CLK_PCM2 131
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#define CLK_PCM1 132
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#define CLK_PCM0 133
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#define CLK_SYSCON 134
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#define CLK_GPIO 135
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#define CLK_TSADC 136
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#define CLK_PWM 137
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#define CLK_WDT 138
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#define CLK_KEYIF 139
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#define CLK_UART3 140
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#define CLK_UART2 141
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#define CLK_UART1 142
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#define CLK_UART0 143
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#define CLK_SYSTIMER 144
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#define CLK_RTC 145
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#define CLK_SPI1 146
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#define CLK_SPI0 147
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#define CLK_I2C_HDMI_PHY 148
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#define CLK_I2C1 149
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#define CLK_I2C2 150
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#define CLK_I2C0 151
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#define CLK_I2S1 152
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#define CLK_I2S2 153
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#define CLK_I2S0 154
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#define CLK_AC97 155
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#define CLK_SPDIF 156
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#define CLK_TZPC3 157
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#define CLK_TZPC2 158
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#define CLK_TZPC1 159
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#define CLK_TZPC0 160
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#define CLK_SECKEY 161
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#define CLK_IEM_APC 162
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#define CLK_IEM_IEC 163
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#define CLK_CHIPID 164
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#define CLK_JPEG 163
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/* Special clocks*/
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#define SCLK_PWI 164
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#define SCLK_SPDIF 165
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#define SCLK_AUDIO2 166
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#define SCLK_AUDIO1 167
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#define SCLK_AUDIO0 168
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#define SCLK_PWM 169
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#define SCLK_SPI1 170
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#define SCLK_SPI0 171
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#define SCLK_UART3 172
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#define SCLK_UART2 173
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#define SCLK_UART1 174
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#define SCLK_UART0 175
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#define SCLK_MMC3 176
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#define SCLK_MMC2 177
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#define SCLK_MMC1 178
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#define SCLK_MMC0 179
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#define SCLK_FINVPLL 180
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#define SCLK_CSIS 181
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#define SCLK_FIMD 182
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#define SCLK_CAM1 183
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#define SCLK_CAM0 184
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#define SCLK_DAC 185
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#define SCLK_MIXER 186
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#define SCLK_HDMI 187
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#define SCLK_FIMC2 188
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#define SCLK_FIMC1 189
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#define SCLK_FIMC0 190
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#define SCLK_HDMI27M 191
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#define SCLK_HDMIPHY 192
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#define SCLK_USBPHY0 193
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#define SCLK_USBPHY1 194
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/* S5P6442-specific clocks */
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#define MOUT_D0SYNC 195
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#define MOUT_D1SYNC 196
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#define DOUT_MIXER 197
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#define CLK_ETB 198
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#define CLK_ETM 199
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/* CLKOUT */
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#define FOUT_APLL_CLKOUT 200
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#define FOUT_MPLL_CLKOUT 201
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#define DOUT_APLL_CLKOUT 202
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#define MOUT_CLKSEL 203
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#define DOUT_CLKOUT 204
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#define MOUT_CLKOUT 205
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/* Total number of clocks. */
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#define NR_CLKS 206
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#endif /* _DT_BINDINGS_CLOCK_S5PV210_H */
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