/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2016 Rockchip Electronics Co. Ltd.
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* Author: Shawn Lin <shawn.lin@rock-chips.com>
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*/
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#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H
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#define _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H
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/* pll id */
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#define PLL_APLL 0
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#define PLL_DPLL 1
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#define PLL_GPLL 2
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#define ARMCLK 3
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/* sclk gates (special clocks) */
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#define SCLK_SPI0 65
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#define SCLK_NANDC 67
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#define SCLK_SDMMC 68
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#define SCLK_SDIO 69
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#define SCLK_EMMC 71
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#define SCLK_UART0 72
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#define SCLK_UART1 73
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#define SCLK_UART2 74
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#define SCLK_I2S0 75
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#define SCLK_I2S1 76
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#define SCLK_I2S2 77
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#define SCLK_TIMER0 78
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#define SCLK_TIMER1 79
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#define SCLK_SFC 80
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#define SCLK_SDMMC_DRV 81
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#define SCLK_SDIO_DRV 82
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#define SCLK_EMMC_DRV 83
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#define SCLK_SDMMC_SAMPLE 84
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#define SCLK_SDIO_SAMPLE 85
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#define SCLK_EMMC_SAMPLE 86
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#define SCLK_VENC_CORE 87
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#define SCLK_HEVC_CORE 88
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#define SCLK_HEVC_CABAC 89
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#define SCLK_PWM0_PMU 90
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#define SCLK_I2C0_PMU 91
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#define SCLK_WIFI 92
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#define SCLK_CIFOUT 93
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#define SCLK_MIPI_CSI_OUT 94
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#define SCLK_CIF0 95
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#define SCLK_CIF1 96
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#define SCLK_CIF2 97
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#define SCLK_CIF3 98
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#define SCLK_DSP 99
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#define SCLK_DSP_IOP 100
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#define SCLK_DSP_EPP 101
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#define SCLK_DSP_EDP 102
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#define SCLK_DSP_EDAP 103
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#define SCLK_CVBS_HOST 104
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#define SCLK_HDMI_SFR 105
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#define SCLK_HDMI_CEC 106
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#define SCLK_CRYPTO 107
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#define SCLK_SPI 108
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#define SCLK_SARADC 109
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#define SCLK_TSADC 110
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#define SCLK_MAC_PRE 111
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#define SCLK_MAC 112
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#define SCLK_MAC_RX 113
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#define SCLK_MAC_REF 114
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#define SCLK_MAC_REFOUT 115
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#define SCLK_DSP_PFM 116
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#define SCLK_RGA 117
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#define SCLK_I2C1 118
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#define SCLK_I2C2 119
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#define SCLK_I2C3 120
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#define SCLK_PWM 121
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#define SCLK_ISP 122
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#define SCLK_USBPHY 123
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#define SCLK_I2S0_SRC 124
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#define SCLK_I2S1_SRC 125
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#define SCLK_I2S2_SRC 126
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#define SCLK_UART0_SRC 127
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#define SCLK_UART1_SRC 128
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#define SCLK_UART2_SRC 129
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#define DCLK_VOP_SRC 185
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#define DCLK_HDMIPHY 186
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#define DCLK_VOP 187
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/* aclk gates */
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#define ACLK_DMAC 192
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#define ACLK_PRE 193
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#define ACLK_CORE 194
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#define ACLK_ENMCORE 195
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#define ACLK_RKVENC 196
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#define ACLK_RKVDEC 197
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#define ACLK_VPU 198
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#define ACLK_CIF0 199
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#define ACLK_VIO0 200
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#define ACLK_VIO1 201
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#define ACLK_VOP 202
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#define ACLK_IEP 203
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#define ACLK_RGA 204
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#define ACLK_ISP 205
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#define ACLK_CIF1 206
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#define ACLK_CIF2 207
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#define ACLK_CIF3 208
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#define ACLK_PERI 209
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#define ACLK_GMAC 210
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/* pclk gates */
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#define PCLK_GPIO1 256
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#define PCLK_GPIO2 257
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#define PCLK_GPIO3 258
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#define PCLK_GRF 259
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#define PCLK_I2C1 260
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#define PCLK_I2C2 261
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#define PCLK_I2C3 262
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#define PCLK_SPI 263
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#define PCLK_SFC 264
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#define PCLK_UART0 265
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#define PCLK_UART1 266
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#define PCLK_UART2 267
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#define PCLK_TSADC 268
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#define PCLK_PWM 269
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#define PCLK_TIMER 270
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#define PCLK_PERI 271
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#define PCLK_GPIO0_PMU 272
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#define PCLK_I2C0_PMU 273
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#define PCLK_PWM0_PMU 274
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#define PCLK_ISP 275
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#define PCLK_VIO 276
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#define PCLK_MIPI_DSI 277
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#define PCLK_HDMI_CTRL 278
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#define PCLK_SARADC 279
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#define PCLK_DSP_CFG 280
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#define PCLK_BUS 281
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#define PCLK_EFUSE0 282
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#define PCLK_EFUSE1 283
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#define PCLK_WDT 284
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#define PCLK_GMAC 285
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/* hclk gates */
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#define HCLK_I2S0_8CH 320
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#define HCLK_I2S1_2CH 321
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#define HCLK_I2S2_2CH 322
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#define HCLK_NANDC 323
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#define HCLK_SDMMC 324
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#define HCLK_SDIO 325
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#define HCLK_EMMC 326
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#define HCLK_PERI 327
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#define HCLK_SFC 328
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#define HCLK_RKVENC 329
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#define HCLK_RKVDEC 330
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#define HCLK_CIF0 331
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#define HCLK_VIO 332
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#define HCLK_VOP 333
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#define HCLK_IEP 334
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#define HCLK_RGA 335
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#define HCLK_ISP 336
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#define HCLK_CRYPTO_MST 337
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#define HCLK_CRYPTO_SLV 338
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#define HCLK_HOST0 339
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#define HCLK_OTG 340
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#define HCLK_CIF1 341
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#define HCLK_CIF2 342
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#define HCLK_CIF3 343
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#define HCLK_BUS 344
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#define HCLK_VPU 345
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#define CLK_NR_CLKS (HCLK_VPU + 1)
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/* reset id */
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#define SRST_CORE_PO_AD 0
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#define SRST_CORE_AD 1
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#define SRST_L2_AD 2
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#define SRST_CPU_NIU_AD 3
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#define SRST_CORE_PO 4
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#define SRST_CORE 5
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#define SRST_L2 6
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#define SRST_CORE_DBG 8
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#define PRST_DBG 9
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#define RST_DAP 10
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#define PRST_DBG_NIU 11
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#define ARST_STRC_SYS_AD 15
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#define SRST_DDRPHY_CLKDIV 16
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#define SRST_DDRPHY 17
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#define PRST_DDRPHY 18
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#define PRST_HDMIPHY 19
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#define PRST_VDACPHY 20
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#define PRST_VADCPHY 21
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#define PRST_MIPI_CSI_PHY 22
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#define PRST_MIPI_DSI_PHY 23
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#define PRST_ACODEC 24
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#define ARST_BUS_NIU 25
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#define PRST_TOP_NIU 26
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#define ARST_INTMEM 27
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#define HRST_ROM 28
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#define ARST_DMAC 29
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#define SRST_MSCH_NIU 30
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#define PRST_MSCH_NIU 31
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#define PRST_DDRUPCTL 32
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#define NRST_DDRUPCTL 33
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#define PRST_DDRMON 34
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#define HRST_I2S0_8CH 35
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#define MRST_I2S0_8CH 36
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#define HRST_I2S1_2CH 37
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#define MRST_IS21_2CH 38
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#define HRST_I2S2_2CH 39
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#define MRST_I2S2_2CH 40
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#define HRST_CRYPTO 41
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#define SRST_CRYPTO 42
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#define PRST_SPI 43
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#define SRST_SPI 44
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#define PRST_UART0 45
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#define PRST_UART1 46
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#define PRST_UART2 47
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#define SRST_UART0 48
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#define SRST_UART1 49
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#define SRST_UART2 50
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#define PRST_I2C1 51
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#define PRST_I2C2 52
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#define PRST_I2C3 53
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#define SRST_I2C1 54
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#define SRST_I2C2 55
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#define SRST_I2C3 56
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#define PRST_PWM1 58
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#define SRST_PWM1 60
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#define PRST_WDT 61
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#define PRST_GPIO1 62
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#define PRST_GPIO2 63
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#define PRST_GPIO3 64
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#define PRST_GRF 65
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#define PRST_EFUSE 66
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#define PRST_EFUSE512 67
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#define PRST_TIMER0 68
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#define SRST_TIMER0 69
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#define SRST_TIMER1 70
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#define PRST_TSADC 71
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#define SRST_TSADC 72
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#define PRST_SARADC 73
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#define SRST_SARADC 74
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#define HRST_SYSBUS 75
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#define PRST_USBGRF 76
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#define ARST_PERIPH_NIU 80
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#define HRST_PERIPH_NIU 81
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#define PRST_PERIPH_NIU 82
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#define HRST_PERIPH 83
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#define HRST_SDMMC 84
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#define HRST_SDIO 85
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#define HRST_EMMC 86
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#define HRST_NANDC 87
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#define NRST_NANDC 88
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#define HRST_SFC 89
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#define SRST_SFC 90
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#define ARST_GMAC 91
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#define HRST_OTG 92
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#define SRST_OTG 93
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#define SRST_OTG_ADP 94
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#define HRST_HOST0 95
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#define HRST_HOST0_AUX 96
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#define HRST_HOST0_ARB 97
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#define SRST_HOST0_EHCIPHY 98
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#define SRST_HOST0_UTMI 99
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#define SRST_USBPOR 100
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#define SRST_UTMI0 101
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#define SRST_UTMI1 102
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#define ARST_VIO0_NIU 102
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#define ARST_VIO1_NIU 103
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#define HRST_VIO_NIU 104
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#define PRST_VIO_NIU 105
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#define ARST_VOP 106
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#define HRST_VOP 107
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#define DRST_VOP 108
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#define ARST_IEP 109
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#define HRST_IEP 110
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#define ARST_RGA 111
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#define HRST_RGA 112
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#define SRST_RGA 113
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#define PRST_CVBS 114
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#define PRST_HDMI 115
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#define SRST_HDMI 116
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#define PRST_MIPI_DSI 117
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#define ARST_ISP_NIU 118
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#define HRST_ISP_NIU 119
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#define HRST_ISP 120
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#define SRST_ISP 121
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#define ARST_VIP0 122
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#define HRST_VIP0 123
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#define PRST_VIP0 124
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#define ARST_VIP1 125
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#define HRST_VIP1 126
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#define PRST_VIP1 127
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#define ARST_VIP2 128
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#define HRST_VIP2 129
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#define PRST_VIP2 120
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#define ARST_VIP3 121
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#define HRST_VIP3 122
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#define PRST_VIP4 123
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#define PRST_CIF1TO4 124
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#define SRST_CVBS_CLK 125
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#define HRST_CVBS 126
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#define ARST_VPU_NIU 140
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#define HRST_VPU_NIU 141
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#define ARST_VPU 142
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#define HRST_VPU 143
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#define ARST_RKVDEC_NIU 144
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#define HRST_RKVDEC_NIU 145
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#define ARST_RKVDEC 146
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#define HRST_RKVDEC 147
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#define SRST_RKVDEC_CABAC 148
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#define SRST_RKVDEC_CORE 149
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#define ARST_RKVENC_NIU 150
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#define HRST_RKVENC_NIU 151
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#define ARST_RKVENC 152
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#define HRST_RKVENC 153
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#define SRST_RKVENC_CORE 154
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#define SRST_DSP_CORE 156
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#define SRST_DSP_SYS 157
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#define SRST_DSP_GLOBAL 158
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#define SRST_DSP_OECM 159
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#define PRST_DSP_IOP_NIU 160
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#define ARST_DSP_EPP_NIU 161
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#define ARST_DSP_EDP_NIU 162
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#define PRST_DSP_DBG_NIU 163
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#define PRST_DSP_CFG_NIU 164
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#define PRST_DSP_GRF 165
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#define PRST_DSP_MAILBOX 166
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#define PRST_DSP_INTC 167
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#define PRST_DSP_PFM_MON 169
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#define SRST_DSP_PFM_MON 170
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#define ARST_DSP_EDAP_NIU 171
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#define SRST_PMU 172
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#define SRST_PMU_I2C0 173
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#define PRST_PMU_I2C0 174
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#define PRST_PMU_GPIO0 175
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#define PRST_PMU_INTMEM 176
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#define PRST_PMU_PWM0 177
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#define SRST_PMU_PWM0 178
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#define PRST_PMU_GRF 179
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#define SRST_PMU_NIU 180
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#define SRST_PMU_PVTM 181
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#define ARST_DSP_EDP_PERF 184
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#define ARST_DSP_EPP_PERF 185
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#endif /* _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H */
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