/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2022 Rockchip Electronics Co. Ltd.
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* Author: Elaine Zhang <zhangqing@rock-chips.com>
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*/
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#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1106_H
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#define _DT_BINDINGS_CLK_ROCKCHIP_RV1106_H
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/* pll clocks */
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#define PLL_APLL 1
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#define PLL_DPLL 2
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#define PLL_CPLL 3
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#define PLL_GPLL 4
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#define ARMCLK 5
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/* clk (clocks) */
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#define PCLK_DDRPHY 11
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#define PCLK_DDR_ROOT 12
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#define PCLK_DDRMON 13
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#define CLK_TIMER_DDRMON 14
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#define PCLK_DDRC 15
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#define PCLK_DFICTRL 16
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#define ACLK_DDR_ROOT 17
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#define ACLK_SYS_SHRM 18
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#define HCLK_NPU_ROOT 19
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#define ACLK_NPU_ROOT 20
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#define PCLK_NPU_ROOT 21
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#define HCLK_RKNN 22
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#define ACLK_RKNN 23
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#define PCLK_ACODEC 24
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#define MCLK_ACODEC_TX 25
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#define CLK_CORE_CRYPTO 27
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#define CLK_PKA_CRYPTO 28
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#define ACLK_CRYPTO 29
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#define HCLK_CRYPTO 30
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#define ACLK_DECOM 31
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#define PCLK_DECOM 32
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#define DCLK_DECOM 33
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#define ACLK_DMAC 34
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#define PCLK_DSM 35
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#define MCLK_DSM 36
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#define CCLK_SRC_EMMC 37
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#define HCLK_EMMC 38
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#define PCLK_GPIO4 39
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#define DBCLK_GPIO4 40
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#define PCLK_I2C0 41
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#define CLK_I2C0 42
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#define PCLK_I2C2 43
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#define CLK_I2C2 44
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#define PCLK_I2C3 45
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#define CLK_I2C3 46
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#define PCLK_I2C4 47
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#define CLK_I2C4 48
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#define HCLK_I2S0 49
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#define PCLK_DFT2APB 50
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#define HCLK_IVE 51
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#define ACLK_IVE 52
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#define PCLK_PWM0_PERI 53
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#define CLK_PWM0_PERI 54
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#define CLK_CAPTURE_PWM0_PERI 55
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#define PCLK_PERI_ROOT 56
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#define ACLK_PERI_ROOT 57
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#define HCLK_PERI_ROOT 58
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#define CLK_TIMER_ROOT 59
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#define ACLK_BUS_ROOT 60
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#define HCLK_SFC 61
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#define SCLK_SFC 62
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#define PCLK_UART0 63
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#define CLK_PVTM_CORE 64
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#define PCLK_UART1 65
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#define CLK_CORE_MCU_RTC 66
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#define PCLK_PWM1_PERI 67
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#define CLK_PWM1_PERI 68
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#define CLK_CAPTURE_PWM1_PERI 69
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#define PCLK_PWM2_PERI 70
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#define CLK_PWM2_PERI 71
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#define CLK_CAPTURE_PWM2_PERI 72
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#define HCLK_BOOTROM 73
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#define HCLK_SAI 74
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#define MCLK_SAI 75
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#define PCLK_SARADC 76
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#define CLK_SARADC 77
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#define PCLK_SPI1 78
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#define CLK_SPI1 79
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#define PCLK_STIMER 80
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#define CLK_STIMER0 81
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#define CLK_STIMER1 82
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#define PCLK_TIMER 83
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#define CLK_TIMER0 84
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#define CLK_TIMER1 85
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#define CLK_TIMER2 86
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#define CLK_TIMER3 87
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#define CLK_TIMER4 88
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#define CLK_TIMER5 89
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#define HCLK_TRNG_NS 90
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#define HCLK_TRNG_S 91
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#define PCLK_UART2 92
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#define HCLK_CPU 93
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#define PCLK_UART3 94
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#define CLK_CORE_MCU 95
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#define PCLK_UART4 96
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#define PCLK_DDR_HWLP 97
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#define PCLK_UART5 98
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#define ACLK_USBOTG 100
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#define CLK_REF_USBOTG 101
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#define CLK_UTMI_USBOTG 102
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#define PCLK_USBPHY 103
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#define CLK_REF_USBPHY 104
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#define PCLK_WDT_NS 105
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#define TCLK_WDT_NS 106
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#define PCLK_WDT_S 107
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#define TCLK_WDT_S 108
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#define CLK_DDR_FAIL_SAFE 109
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#define XIN_OSC0_DIV 110
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#define CLK_DEEPSLOW 111
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#define PCLK_PMU_GPIO0 112
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#define DBCLK_PMU_GPIO0 113
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#define CLK_PMU 114
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#define PCLK_PMU 115
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#define PCLK_PMU_HP_TIMER 116
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#define CLK_PMU_HP_TIMER 117
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#define CLK_PMU_32K_HP_TIMER 118
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#define PCLK_I2C1 119
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#define CLK_I2C1 120
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#define PCLK_PMU_IOC 121
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#define PCLK_PMU_MAILBOX 122
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#define CLK_PMU_MCU 123
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#define CLK_PMU_MCU_RTC 124
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#define CLK_PMU_MCU_JTAG 125
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#define CLK_PVTM_PMU 126
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#define PCLK_PVTM_PMU 127
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#define CLK_REFOUT 128
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#define CLK_100M_PMU 129
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#define PCLK_PMU_ROOT 130
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#define HCLK_PMU_ROOT 131
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#define HCLK_PMU_SRAM 132
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#define PCLK_PMU_WDT 133
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#define TCLK_PMU_WDT 134
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#define CLK_DFICTRL 135
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#define CLK_DDRMON 136
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#define CLK_DDR_PHY 137
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#define ACLK_DDRC 138
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#define CLK_CORE_DDRC_SRC 139
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#define CLK_CORE_DDRC 140
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#define CLK_50M_SRC 141
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#define CLK_100M_SRC 142
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#define CLK_150M_SRC 143
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#define CLK_200M_SRC 144
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#define CLK_250M_SRC 145
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#define CLK_300M_SRC 146
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#define CLK_339M_SRC 147
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#define CLK_400M_SRC 148
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#define CLK_450M_SRC 149
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#define CLK_500M_SRC 150
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#define CLK_I2S0_8CH_TX_SRC 151
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#define CLK_I2S0_8CH_TX_FRAC 152
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#define CLK_I2S0_8CH_TX 153
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#define CLK_I2S0_8CH_RX_SRC 154
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#define CLK_I2S0_8CH_RX_FRAC 155
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#define CLK_I2S0_8CH_RX 156
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#define I2S0_8CH_MCLKOUT 157
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#define MCLK_I2S0_8CH_RX 158
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#define MCLK_I2S0_8CH_TX 159
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#define CLK_REF_MIPI0_SRC 160
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#define CLK_REF_MIPI0_FRAC 161
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#define CLK_REF_MIPI0_OUT 162
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#define CLK_REF_MIPI1_SRC 163
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#define CLK_REF_MIPI1_FRAC 164
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#define MCLK_REF_MIPI0 165
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#define MCLK_REF_MIPI1 166
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#define CLK_REF_MIPI0 167
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#define CLK_REF_MIPI1 168
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#define CLK_UART0_SRC 169
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#define CLK_UART0_FRAC 170
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#define CLK_UART0 171
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#define SCLK_UART0 172
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#define CLK_UART1_SRC 173
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#define CLK_UART1_FRAC 174
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#define CLK_UART1 175
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#define SCLK_UART1 176
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#define CLK_UART2_SRC 177
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#define CLK_UART2_FRAC 178
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#define CLK_UART2 179
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#define SCLK_UART2 180
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#define CLK_UART3_SRC 181
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#define CLK_UART3_FRAC 182
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#define CLK_UART3 183
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#define SCLK_UART3 184
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#define CLK_UART4_SRC 185
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#define CLK_UART4_FRAC 186
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#define CLK_UART4 187
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#define SCLK_UART4 188
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#define CLK_UART5_SRC 189
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#define CLK_UART5_FRAC 190
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#define CLK_UART5 191
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#define SCLK_UART5 192
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#define CLK_VICAP_M0_SRC 193
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#define CLK_VICAP_M0_FRAC 194
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#define CLK_VICAP_M0 195
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#define SCLK_VICAP_M0 196
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#define CLK_VICAP_M1_SRC 197
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#define CLK_VICAP_M1_FRAC 198
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#define CLK_VICAP_M1 199
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#define SCLK_VICAP_M1 200
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#define DCLK_VOP_SRC 201
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#define PCLK_CRU 202
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#define PCLK_TOP_ROOT 203
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#define PCLK_SPI0 204
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#define CLK_SPI0 205
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#define SCLK_IN_SPI0 206
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#define CLK_UART_DETN_FLT 207
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#define HCLK_VEPU 208
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#define ACLK_VEPU 209
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#define CLK_CORE_VEPU 210
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#define CLK_CORE_VEPU_DVBM 211
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#define PCLK_GPIO1 212
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#define DBCLK_GPIO1 213
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#define HCLK_VEPU_PP 214
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#define ACLK_VEPU_PP 215
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#define HCLK_VEPU_ROOT 216
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#define ACLK_VEPU_COM_ROOT 217
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#define ACLK_VEPU_ROOT 218
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#define PCLK_VEPU_ROOT 219
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#define PCLK_VICAP_VEPU 220
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#define PCLK_CSIHOST0 221
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#define CLK_RXBYTECLKHS_0 222
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#define PCLK_CSIHOST1 223
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#define CLK_RXBYTECLKHS_1 224
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#define PCLK_GPIO3 225
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#define DBCLK_GPIO3 226
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#define HCLK_ISP3P2 227
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#define ACLK_ISP3P2 228
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#define CLK_CORE_ISP3P2 229
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#define PCLK_MIPICSIPHY 230
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#define CCLK_SRC_SDMMC 231
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#define HCLK_SDMMC 232
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#define CLK_SDMMC_DETN_FLT 233
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#define HCLK_VI_ROOT 234
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#define ACLK_VI_ROOT 235
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#define PCLK_VI_ROOT 236
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#define PCLK_VI_RTC_ROOT 237
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#define PCLK_VI_RTC_TEST 238
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#define PCLK_VI_RTC_PHY 239
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#define DCLK_VICAP 240
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#define PCLK_VICAP 241
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#define ACLK_VICAP 242
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#define HCLK_VICAP 243
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#define I0CLK_VICAP 244
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#define I1CLK_VICAP 245
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#define RX0PCLK_VICAP 246
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#define RX1PCLK_VICAP 247
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#define ISP0CLK_VICAP 248
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#define PCLK_GPIO2 249
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#define DBCLK_GPIO2 250
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#define ACLK_MAC 251
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#define PCLK_MAC 252
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#define CLK_GMAC0_50M_O 253
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#define CLK_GMAC0_TX_50M_O 254
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#define CLK_GMAC0_REF_50M 255
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#define CLK_GMAC0_TX_50M 256
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#define CLK_GMAC0_RX_50M 257
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#define ACLK_MAC_ROOT 258
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#define CLK_MACPHY 259
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#define CLK_OTPC_ARB 260
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#define PCLK_OTPC_NS 261
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#define CLK_SBPI_OTPC_NS 262
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#define CLK_USER_OTPC_NS 263
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#define PCLK_OTPC_S 264
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#define CLK_SBPI_OTPC_S 265
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#define CLK_USER_OTPC_S 266
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#define PCLK_OTP_MASK 267
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#define CLK_PMC_OTP 268
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#define HCLK_RGA2E 269
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#define ACLK_RGA2E 270
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#define CLK_CORE_RGA2E 271
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#define CCLK_SRC_SDIO 272
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#define HCLK_SDIO 273
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#define PCLK_TSADC 274
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#define CLK_TSADC 275
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#define CLK_TSADC_TSEN 276
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#define ACLK_VO_ROOT 277
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#define HCLK_VO_ROOT 278
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#define PCLK_VO_ROOT 279
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#define ACLK_VOP_ROOT 280
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#define HCLK_VOP 281
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#define DCLK_VOP 282
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#define ACLK_VOP 283
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#define CLK_RTC_32K 284
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#define PCLK_MAILBOX 291
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#define CLK_NR_CLKS (PCLK_MAILBOX + 1)
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#define SCLK_EMMC_DRV 1
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#define SCLK_EMMC_SAMPLE 2
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#define SCLK_SDMMC_DRV 3
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#define SCLK_SDMMC_SAMPLE 4
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#define SCLK_SDIO_DRV 5
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#define SCLK_SDIO_SAMPLE 6
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#define CLK_NR_GRF_CLKS (SCLK_SDIO_SAMPLE + 1)
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/********Name=PMUSOFTRST_CON00,Offset=0xA00********/
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#define SRST_P_I2C1 3
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#define SRST_I2C1 4
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#define SRST_H_PMU_BIU 6
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#define SRST_P_PMU_BIU 7
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#define SRST_H_PMU_SRAM 8
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#define SRST_PMU_MCU 9
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#define SRST_PMU_MCU_PWRUP 10
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#define SRST_PMU_MCU_CPU 11
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#define SRST_T_PMU_MCU_CPU 12
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/********Name=PMUSOFTRST_CON01,Offset=0xA04********/
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#define SRST_P_PMU_GPIO0 18
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#define SRST_PMU_GPIO0 19
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#define SRST_PVTM_PMU 20
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#define SRST_P_PVTM_PMU 21
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#define SRST_DDR_FAIL_SAFE 31
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/********Name=PMUSOFTRST_CON02,Offset=0xA08********/
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#define SRST_P_PMU_HP_TIMER 32
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#define SRST_PMU_HP_TIMER 33
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#define SRST_PMU_32K_HP_TIMER 34
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#define SRST_P_PMU_IOC 35
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#define SRST_P_PMU_CRU 36
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#define SRST_P_PMU_GRF 37
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#define SRST_P_PMU_SGRF 38
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#define SRST_P_PMU_SGRF_REMAP 39
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#define SRST_P_PMU_WDT 40
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#define SRST_T_PMU_WDT 41
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#define SRST_P_PMU_MAILBOX 42
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#define SRST_WRITE_ENABLE 48
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/********Name=SOFTRST_CON02,Offset=0x10A08********/
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#define SRST_REF_PVTPLL_0 262183
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#define SRST_REF_PVTPLL_1 262184
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#define SRST_P_CRU 262186
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#define SRST_P_CRU_BIU 262187
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/********Name=PERISOFTRST_CON00,Offset=0x12A00********/
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#define SRST_P_PERI_BIU 294916
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#define SRST_A_PERI_BIU 294917
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#define SRST_H_PERI_BIU 294918
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#define SRST_H_BOOTROM 294919
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#define SRST_P_TIMER 294920
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#define SRST_TIMER0 294921
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#define SRST_TIMER1 294922
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#define SRST_TIMER2 294923
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#define SRST_TIMER3 294924
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#define SRST_TIMER4 294925
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#define SRST_TIMER5 294926
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#define SRST_P_STIMER 294927
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/********Name=PERISOFTRST_CON01,Offset=0x12A04********/
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#define SRST_STIMER0 294928
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#define SRST_STIMER1 294929
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#define SRST_P_WDT_NS 294930
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#define SRST_T_WDT_NS 294931
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#define SRST_P_WDT_S 294932
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#define SRST_T_WDT_S 294933
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#define SRST_P_I2C0 294934
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#define SRST_I2C0 294935
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#define SRST_P_I2C2 294938
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#define SRST_I2C2 294939
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#define SRST_P_I2C3 294940
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#define SRST_I2C3 294941
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#define SRST_P_I2C4 294942
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#define SRST_I2C4 294943
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/********Name=PERISOFTRST_CON02,Offset=0x12A08********/
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#define SRST_P_GPIO4 294944
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#define SRST_GPIO4 294945
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#define SRST_P_PERI_IOC 294946
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#define SRST_P_UART2 294947
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#define SRST_S_UART2 294950
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#define SRST_P_UART3 294951
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#define SRST_S_UART3 294954
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#define SRST_P_UART4 294955
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#define SRST_S_UART4 294958
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#define SRST_P_UART5 294959
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/********Name=PERISOFTRST_CON03,Offset=0x12A0C********/
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#define SRST_S_UART5 294962
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#define SRST_P_SARADC 294963
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#define SRST_SARADC 294964
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#define SRST_SARADC_PHY 294965
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#define SRST_P_SPI1 294966
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#define SRST_SPI1 294967
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#define SRST_H_TRNG_NS 294969
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#define SRST_H_TRNG_S 294970
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#define SRST_CORE_CRYPTO 294971
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#define SRST_PKA_CRYPTO 294972
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#define SRST_A_CRYPTO 294973
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#define SRST_H_CRYPTO 294974
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#define SRST_P_PWM1_PERI 294975
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/********Name=PERISOFTRST_CON04,Offset=0x12A10********/
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#define SRST_PWM1_PERI 294976
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#define SRST_P_PWM2_PERI 294978
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#define SRST_PWM2_PERI 294979
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#define SRST_P_PERI_GRF 294981
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#define SRST_P_PERI_CRU 294982
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#define SRST_A_USBOTG 294983
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#define SRST_A_BUS_BIU 294986
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#define SRST_H_EMMC 294989
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#define SRST_H_SFC 294990
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/********Name=PERISOFTRST_CON05,Offset=0x12A14********/
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#define SRST_S_SFC 294992
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#define SRST_P_USBPHY 294993
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#define SRST_USBPHY_POR 294994
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#define SRST_USBPHY_OTG 294995
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#define SRST_A_DMAC 295000
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#define SRST_A_DECOM 295001
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#define SRST_P_DECOM 295002
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#define SRST_D_DECOM 295003
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#define SRST_P_PERI_SGRF 295004
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#define SRST_H_SAI 295005
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#define SRST_M_SAI 295006
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#define SRST_M_I2S0_8CH_TX 295007
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/********Name=PERISOFTRST_CON06,Offset=0x12A18********/
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#define SRST_H_I2S0 295008
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#define SRST_M_DSM 295009
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#define SRST_P_DSM 295010
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#define SRST_P_ACODEC 295011
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#define SRST_M_I2S0_8CH_RX 295014
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#define SRST_P_DFT2APB 295015
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#define SRST_H_IVE 295017
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#define SRST_A_IVE 295018
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#define SRST_P_UART0 295019
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#define SRST_S_UART0 295022
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#define SRST_P_UART1 295023
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/********Name=PERISOFTRST_CON07,Offset=0x12A1C********/
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#define SRST_S_UART1 295026
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#define SRST_P_PWM0_PERI 295027
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#define SRST_PWM0_PERI 295028
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/********Name=VISOFTRST_CON00,Offset=0x14A00********/
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#define SRST_H_VI_BIU 327684
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#define SRST_A_VI_BIU 327685
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#define SRST_P_VI_BIU 327686
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#define SRST_CORE_ISP3P2 327689
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#define SRST_D_VICAP 327690
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#define SRST_P_VICAP 327691
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#define SRST_A_VICAP 327692
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#define SRST_H_VICAP 327693
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#define SRST_VICAP_I0 327694
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#define SRST_VICAP_I1 327695
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/********Name=VISOFTRST_CON01,Offset=0x14A04********/
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#define SRST_VICAP_RX0 327696
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#define SRST_VICAP_RX1 327697
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#define SRST_VICAP_ISP0 327698
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#define SRST_P_CSIHOST0 327700
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#define SRST_P_CSIHOST1 327702
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#define SRST_H_SDMMC 327708
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#define SRST_SDMMC_DETN_FLT 327709
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#define SRST_P_MIPICSIPHY 327710
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#define SRST_P_GPIO3 327711
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/********Name=VISOFTRST_CON02,Offset=0x14A08********/
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#define SRST_GPIO3 327712
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#define SRST_P_VI_IOC 327713
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#define SRST_P_VI_GRF 327714
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#define SRST_P_VI_SGRF 327715
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#define SRST_P_VI_CRU 327716
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#define SRST_P_VI_RTC_TEST 327717
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#define SRST_P_VI_RTC_NIU 327719
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/********Name=NPUSOFTRST_CON00,Offset=0x16A00********/
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#define SRST_H_NPU_BIU 360451
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#define SRST_A_NPU_BIU 360452
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#define SRST_P_NPU_BIU 360453
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#define SRST_P_NPU_CRU 360454
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#define SRST_P_NPU_SGRF 360455
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#define SRST_P_NPU_GRF 360456
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#define SRST_H_RKNN 360457
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#define SRST_A_RKNN 360458
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/********Name=CORESOFTRST_CON00,Offset=0x18A00********/
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#define SRST_NCOREPORESET 393217
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#define SRST_NCORESET 393218
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#define SRST_NDBGRESET 393219
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#define SRST_NL2RESET 393220
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#define SRST_A_M_CORE_BIU 393221
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#define SRST_P_DBG 393222
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#define SRST_POT_DBG 393223
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#define SRST_NT_DBG 393224
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#define SRST_P_CORE_GRF 393227
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#define SRST_H_CPU_BIU 393228
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#define SRST_P_CPU_BIU 393229
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#define SRST_PVTM_CORE 393230
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#define SRST_P_PVTM_CORE 393231
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/********Name=CORESOFTRST_CON01,Offset=0x18A04********/
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#define SRST_REF_PVTPLL_CORE 393232
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#define SRST_CORE_MCU 393233
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#define SRST_CORE_MCU_PWRUP 393234
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#define SRST_CORE_MCU_CPU 393235
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#define SRST_T_CORE_MCU_CPU 393236
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#define SRST_MCU_BIU 393237
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#define SRST_P_MAILBOX 393240
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#define SRST_P_INTMUX 393241
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#define SRST_P_CORE_CRU 393242
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#define SRST_P_CORE_SGRF 393243
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#define SRST_H_CACHE 393244
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/********Name=VEPUSOFTRST_CON00,Offset=0x1AA00********/
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#define SRST_H_VEPU_BIU 425988
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#define SRST_A_VEPU_BIU 425989
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#define SRST_A_VEPU_COM_BIU 425990
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#define SRST_P_VEPU_BIU 425991
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#define SRST_H_VEPU 425992
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#define SRST_A_VEPU 425993
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#define SRST_CORE_VEPU 425994
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#define SRST_H_VEPU_PP 425995
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#define SRST_A_VEPU_PP 425996
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#define SRST_CORE_VEPU_DVBM 425997
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#define SRST_P_VICAP_VEPU 425998
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#define SRST_P_GPIO1 425999
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/********Name=VEPUSOFTRST_CON01,Offset=0x1AA04********/
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#define SRST_GPIO1 426000
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#define SRST_P_VEPU_IOC 426001
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#define SRST_P_SPI0 426002
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#define SRST_SPI0 426003
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#define SRST_P_VEPU_CRU 426005
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#define SRST_P_VEPU_SGRF 426006
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#define SRST_P_VEPU_GRF 426007
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#define SRST_UART_DETN_FLT 426008
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/********Name=VOSOFTRST_CON00,Offset=0x1CA00********/
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#define SRST_A_VO_BIU 458755
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#define SRST_H_VO_BIU 458756
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#define SRST_H_RGA2E 458759
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#define SRST_A_RGA2E 458760
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#define SRST_CORE_RGA2E 458761
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#define SRST_P_VO_GRF 458762
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#define SRST_A_VOP_BIU 458764
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#define SRST_H_VOP 458765
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#define SRST_D_VOP 458766
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#define SRST_A_VOP 458767
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/********Name=VOSOFTRST_CON01,Offset=0x1CA04********/
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#define SRST_P_MAC_BIU 458774
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#define SRST_A_MAC_BIU 458775
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#define SRST_A_MAC 458776
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#define SRST_P_VO_SGRF 458780
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#define SRST_P_VO_CRU 458781
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#define SRST_H_SDIO 458783
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/********Name=VOSOFTRST_CON02,Offset=0x1CA08********/
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#define SRST_P_TSADC 458784
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#define SRST_TSADC 458785
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#define SRST_P_OTPC_NS 458787
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#define SRST_SBPI_OTPC_NS 458789
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#define SRST_USER_OTPC_NS 458790
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#define SRST_P_OTPC_S 458791
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#define SRST_SBPI_OTPC_S 458793
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#define SRST_USER_OTPC_S 458794
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#define SRST_OTPC_ARB 458795
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#define SRST_MACPHY 458797
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#define SRST_P_OTP_MASK 458798
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#define SRST_PMC_OTP 458799
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/********Name=VOSOFTRST_CON03,Offset=0x1CA0C********/
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#define SRST_P_GPIO2 458800
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#define SRST_GPIO2 458801
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#define SRST_P_VO_IOC 458802
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/********Name=DDRSOFTRST_CON00,Offset=0x1EA00********/
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#define SRST_P_DDR_BIU 491522
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#define SRST_P_DDRC 491525
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#define SRST_P_DDRMON 491527
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#define SRST_TIMER_DDRMON 491528
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#define SRST_P_DFICTRL 491531
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#define SRST_A_SYS_SHRM 491533
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#define SRST_A_SHRM_NIU 491534
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#define SRST_P_DDR_GRF 491535
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/********Name=DDRSOFTRST_CON01,Offset=0x1EA04********/
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#define SRST_P_DDR_CRU 491536
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#define SRST_P_DDR_HWLP 491538
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#define SRST_P_DDRPHY 491539
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/********Name=SUBDDRSOFTRST_CON00,Offset=0x1FA00********/
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#define SRST_MSCH_BIU 507904
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#define SRST_A_DDRC 507905
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#define SRST_CORE_DDRC 507907
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#define SRST_DDRMON 507908
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#define SRST_DFICTRL 507909
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#define SRST_DDR_PHY 507910
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#endif
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