/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2017 Rockchip Electronics Co. Ltd.
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* Author: Elaine <zhangqing@rock-chips.com>
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*/
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#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H
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#define _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H
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/* core clocks */
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#define PLL_APLL 1
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#define PLL_DPLL 2
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#define PLL_CPLL 3
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#define PLL_GPLL 4
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#define ARMCLK 5
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#define PLL_GPLL_DIV2 6
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#define PLL_GPLL_DIV3 7
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/* sclk gates (special clocks) */
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#define SCLK_SPI0 65
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#define SCLK_NANDC 67
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#define SCLK_SDMMC 68
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#define SCLK_SDIO 69
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#define SCLK_EMMC 71
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#define SCLK_UART0 77
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#define SCLK_UART1 78
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#define SCLK_UART2 79
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#define SCLK_I2S0 80
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#define SCLK_I2S1 81
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#define SCLK_SPDIF 83
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#define SCLK_TIMER0 85
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#define SCLK_TIMER1 86
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#define SCLK_TIMER2 87
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#define SCLK_TIMER3 88
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#define SCLK_TIMER4 89
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#define SCLK_TIMER5 90
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#define SCLK_SARADC 91
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#define SCLK_I2S_OUT 113
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#define SCLK_SDMMC_DRV 114
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#define SCLK_SDIO_DRV 115
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#define SCLK_EMMC_DRV 117
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#define SCLK_SDMMC_SAMPLE 118
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#define SCLK_SDIO_SAMPLE 119
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#define SCLK_EMMC_SAMPLE 121
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#define SCLK_VOP 122
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#define SCLK_MAC_SRC 124
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#define SCLK_MAC 126
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#define SCLK_MAC_REFOUT 127
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#define SCLK_MAC_REF 128
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#define SCLK_MAC_RX 129
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#define SCLK_MAC_TX 130
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#define SCLK_HEVC_CORE 134
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#define SCLK_RGA 135
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#define SCLK_CRYPTO 138
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#define SCLK_TSP 139
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#define SCLK_OTGPHY0 142
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#define SCLK_OTGPHY1 143
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#define SCLK_DDRC 144
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#define SCLK_PVTM_FUNC 145
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#define SCLK_PVTM_CORE 146
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#define SCLK_PVTM_GPU 147
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#define SCLK_MIPI_24M 148
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#define SCLK_PVTM 149
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#define SCLK_CIF_SRC 150
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#define SCLK_CIF_OUT_SRC 151
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#define SCLK_CIF_OUT 152
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#define SCLK_SFC 153
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#define SCLK_USB480M 154
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#define SCLK_HSADC_TSP 155
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/* dclk gates */
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#define DCLK_VOP 190
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#define DCLK_EBC 191
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/* aclk gates */
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#define ACLK_VIO0 192
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#define ACLK_VIO1 193
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#define ACLK_DMAC 194
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#define ACLK_CPU 195
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#define ACLK_VEPU 196
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#define ACLK_VDPU 197
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#define ACLK_CIF 198
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#define ACLK_IEP 199
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#define ACLK_LCDC0 204
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#define ACLK_RGA 205
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#define ACLK_PERI 210
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#define ACLK_VOP 211
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#define ACLK_GMAC 212
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#define ACLK_GPU 213
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/* pclk gates */
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#define PCLK_SARADC 318
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#define PCLK_WDT 319
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#define PCLK_GPIO0 320
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#define PCLK_GPIO1 321
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#define PCLK_GPIO2 322
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#define PCLK_GPIO3 323
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#define PCLK_VIO_H2P 324
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#define PCLK_MIPI 325
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#define PCLK_EFUSE 326
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#define PCLK_HDMI 327
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#define PCLK_ACODEC 328
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#define PCLK_GRF 329
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#define PCLK_I2C0 332
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#define PCLK_I2C1 333
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#define PCLK_I2C2 334
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#define PCLK_I2C3 335
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#define PCLK_SPI0 338
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#define PCLK_UART0 341
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#define PCLK_UART1 342
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#define PCLK_UART2 343
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#define PCLK_TSADC 344
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#define PCLK_PWM 350
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#define PCLK_TIMER 353
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#define PCLK_CPU 354
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#define PCLK_PERI 363
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#define PCLK_GMAC 367
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#define PCLK_PMU_PRE 368
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#define PCLK_SIM_CARD 369
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#define PCLK_MIPIPHY 370
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/* hclk gates */
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#define HCLK_SFC 439
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#define HCLK_SPDIF 440
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#define HCLK_GPS 441
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#define HCLK_USBHOST 442
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#define HCLK_I2S_8CH 443
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#define HCLK_I2S_2CH 444
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#define HCLK_VOP 452
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#define HCLK_NANDC 453
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#define HCLK_SDMMC 456
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#define HCLK_SDIO 457
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#define HCLK_EMMC 459
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#define HCLK_CPU 460
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#define HCLK_VEPU 461
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#define HCLK_VDPU 462
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#define HCLK_LCDC0 463
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#define HCLK_EBC 465
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#define HCLK_VIO 466
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#define HCLK_RGA 467
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#define HCLK_IEP 468
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#define HCLK_VIO_H2P 469
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#define HCLK_CIF 470
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#define HCLK_HOST2 473
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#define HCLK_OTG 474
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#define HCLK_TSP 475
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#define HCLK_CRYPTO 476
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#define HCLK_PERI 478
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#define CLK_NR_CLKS (HCLK_PERI + 1)
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/* soft-reset indices */
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#define SRST_CORE0_PO 0
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#define SRST_CORE1_PO 1
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#define SRST_CORE2_PO 2
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#define SRST_CORE3_PO 3
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#define SRST_CORE0 4
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#define SRST_CORE1 5
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#define SRST_CORE2 6
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#define SRST_CORE3 7
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#define SRST_CORE0_DBG 8
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#define SRST_CORE1_DBG 9
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#define SRST_CORE2_DBG 10
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#define SRST_CORE3_DBG 11
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#define SRST_TOPDBG 12
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#define SRST_ACLK_CORE 13
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#define SRST_STRC_SYS_A 14
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#define SRST_L2C 15
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#define SRST_CPUSYS_H 18
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#define SRST_AHB2APBSYS_H 19
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#define SRST_SPDIF 20
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#define SRST_INTMEM 21
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#define SRST_ROM 22
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#define SRST_PERI_NIU 23
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#define SRST_I2S_2CH 24
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#define SRST_I2S_8CH 25
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#define SRST_GPU_PVTM 26
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#define SRST_FUNC_PVTM 27
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#define SRST_CORE_PVTM 29
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#define SRST_EFUSE_P 30
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#define SRST_ACODEC_P 31
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#define SRST_GPIO0 32
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#define SRST_GPIO1 33
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#define SRST_GPIO2 34
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#define SRST_GPIO3 35
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#define SRST_MIPIPHY_P 36
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#define SRST_UART0 39
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#define SRST_UART1 40
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#define SRST_UART2 41
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#define SRST_I2C0 43
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#define SRST_I2C1 44
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#define SRST_I2C2 45
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#define SRST_I2C3 46
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#define SRST_SFC 47
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#define SRST_PWM 48
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#define SRST_DAP_PO 50
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#define SRST_DAP 51
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#define SRST_DAP_SYS 52
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#define SRST_CRYPTO 53
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#define SRST_GRF 55
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#define SRST_GMAC 56
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#define SRST_PERIPH_SYS_A 57
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#define SRST_PERIPH_SYS_H 58
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#define SRST_PERIPH_SYS_P 59
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#define SRST_SMART_CARD 60
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#define SRST_CPU_PERI 61
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#define SRST_EMEM_PERI 62
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#define SRST_USB_PERI 63
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#define SRST_DMA 64
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#define SRST_GPS 67
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#define SRST_NANDC 68
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#define SRST_USBOTG0 69
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#define SRST_OTGC0 71
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#define SRST_USBOTG1 72
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#define SRST_OTGC1 74
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#define SRST_DDRMSCH 79
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#define SRST_SDMMC 81
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#define SRST_SDIO 82
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#define SRST_EMMC 83
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#define SRST_SPI 84
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#define SRST_WDT 86
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#define SRST_SARADC 87
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#define SRST_DDRPHY 88
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#define SRST_DDRPHY_P 89
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#define SRST_DDRCTRL 90
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#define SRST_DDRCTRL_P 91
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#define SRST_TSP 92
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#define SRST_TSP_CLKIN 93
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#define SRST_HOST0_ECHI 94
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#define SRST_HDMI_P 96
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#define SRST_VIO_ARBI_H 97
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#define SRST_VIO0_A 98
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#define SRST_VIO_BUS_H 99
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#define SRST_VOP_A 100
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#define SRST_VOP_H 101
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#define SRST_VOP_D 102
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#define SRST_UTMI0 103
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#define SRST_UTMI1 104
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#define SRST_USBPOR 105
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#define SRST_IEP_A 106
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#define SRST_IEP_H 107
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#define SRST_RGA_A 108
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#define SRST_RGA_H 109
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#define SRST_CIF0 110
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#define SRST_PMU 111
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#define SRST_VCODEC_A 112
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#define SRST_VCODEC_H 113
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#define SRST_VIO1_A 114
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#define SRST_HEVC_CORE 115
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#define SRST_VCODEC_NIU_A 116
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#define SRST_PMU_NIU_P 117
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#define SRST_LCDC0_S 119
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#define SRST_GPU 120
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#define SRST_GPU_NIU_A 122
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#define SRST_EBC_A 123
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#define SRST_EBC_H 124
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#define SRST_CORE_DBG 128
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#define SRST_DBG_P 129
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#define SRST_TIMER0 130
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#define SRST_TIMER1 131
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#define SRST_TIMER2 132
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#define SRST_TIMER3 133
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#define SRST_TIMER4 134
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#define SRST_TIMER5 135
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#define SRST_VIO_H2P 136
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#define SRST_VIO_MIPI_DSI 137
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#endif
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