/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2018 Renesas Electronics Corp.
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*/
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#ifndef __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__
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#define __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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/* r8a77990 CPG Core Clocks */
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#define R8A77990_CLK_Z2 0
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#define R8A77990_CLK_ZR 1
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#define R8A77990_CLK_ZG 2
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#define R8A77990_CLK_ZTR 3
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#define R8A77990_CLK_ZT 4
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#define R8A77990_CLK_ZX 5
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#define R8A77990_CLK_S0D1 6
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#define R8A77990_CLK_S0D3 7
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#define R8A77990_CLK_S0D6 8
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#define R8A77990_CLK_S0D12 9
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#define R8A77990_CLK_S0D24 10
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#define R8A77990_CLK_S1D1 11
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#define R8A77990_CLK_S1D2 12
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#define R8A77990_CLK_S1D4 13
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#define R8A77990_CLK_S2D1 14
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#define R8A77990_CLK_S2D2 15
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#define R8A77990_CLK_S2D4 16
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#define R8A77990_CLK_S3D1 17
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#define R8A77990_CLK_S3D2 18
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#define R8A77990_CLK_S3D4 19
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#define R8A77990_CLK_S0D6C 20
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#define R8A77990_CLK_S3D1C 21
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#define R8A77990_CLK_S3D2C 22
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#define R8A77990_CLK_S3D4C 23
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#define R8A77990_CLK_LB 24
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#define R8A77990_CLK_CL 25
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#define R8A77990_CLK_ZB3 26
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#define R8A77990_CLK_ZB3D2 27
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#define R8A77990_CLK_CR 28
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#define R8A77990_CLK_CRD2 29
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#define R8A77990_CLK_SD0H 30
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#define R8A77990_CLK_SD0 31
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#define R8A77990_CLK_SD1H 32
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#define R8A77990_CLK_SD1 33
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#define R8A77990_CLK_SD3H 34
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#define R8A77990_CLK_SD3 35
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#define R8A77990_CLK_RPC 36
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#define R8A77990_CLK_RPCD2 37
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#define R8A77990_CLK_ZA2 38
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#define R8A77990_CLK_ZA8 39
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#define R8A77990_CLK_Z2D 40
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#define R8A77990_CLK_CANFD 41
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#define R8A77990_CLK_MSO 42
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#define R8A77990_CLK_R 43
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#define R8A77990_CLK_OSC 44
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#define R8A77990_CLK_LV0 45
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#define R8A77990_CLK_LV1 46
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#define R8A77990_CLK_CSI0 47
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#define R8A77990_CLK_CP 48
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#define R8A77990_CLK_CPEX 49
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#endif /* __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__ */
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