/* SPDX-License-Identifier: GPL-2.0+
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*
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* Copyright (C) 2015 Renesas Electronics Corp.
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*/
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#ifndef __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__
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#define __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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/* r8a7792 CPG Core Clocks */
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#define R8A7792_CLK_Z 0
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#define R8A7792_CLK_ZG 1
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#define R8A7792_CLK_ZTR 2
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#define R8A7792_CLK_ZTRD2 3
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#define R8A7792_CLK_ZT 4
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#define R8A7792_CLK_ZX 5
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#define R8A7792_CLK_ZS 6
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#define R8A7792_CLK_HP 7
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#define R8A7792_CLK_I 8
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#define R8A7792_CLK_B 9
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#define R8A7792_CLK_LB 10
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#define R8A7792_CLK_P 11
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#define R8A7792_CLK_CL 12
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#define R8A7792_CLK_M2 13
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#define R8A7792_CLK_IMP 14
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#define R8A7792_CLK_ZB3 15
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#define R8A7792_CLK_ZB3D2 16
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#define R8A7792_CLK_DDR 17
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#define R8A7792_CLK_SD 18
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#define R8A7792_CLK_MP 19
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#define R8A7792_CLK_QSPI 20
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#define R8A7792_CLK_CP 21
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#define R8A7792_CLK_CPEX 22
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#define R8A7792_CLK_RCAN 23
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#define R8A7792_CLK_R 24
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#define R8A7792_CLK_OSC 25
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#endif /* __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__ */
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