/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2015, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_MSM_MMCC_8996_H
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#define _DT_BINDINGS_CLK_MSM_MMCC_8996_H
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#define MMPLL0_EARLY 0
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#define MMPLL0_PLL 1
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#define MMPLL1_EARLY 2
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#define MMPLL1_PLL 3
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#define MMPLL2_EARLY 4
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#define MMPLL2_PLL 5
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#define MMPLL3_EARLY 6
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#define MMPLL3_PLL 7
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#define MMPLL4_EARLY 8
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#define MMPLL4_PLL 9
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#define MMPLL5_EARLY 10
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#define MMPLL5_PLL 11
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#define MMPLL8_EARLY 12
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#define MMPLL8_PLL 13
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#define MMPLL9_EARLY 14
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#define MMPLL9_PLL 15
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#define AHB_CLK_SRC 16
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#define AXI_CLK_SRC 17
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#define MAXI_CLK_SRC 18
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#define DSA_CORE_CLK_SRC 19
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#define GFX3D_CLK_SRC 20
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#define RBBMTIMER_CLK_SRC 21
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#define ISENSE_CLK_SRC 22
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#define RBCPR_CLK_SRC 23
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#define VIDEO_CORE_CLK_SRC 24
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#define VIDEO_SUBCORE0_CLK_SRC 25
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#define VIDEO_SUBCORE1_CLK_SRC 26
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#define PCLK0_CLK_SRC 27
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#define PCLK1_CLK_SRC 28
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#define MDP_CLK_SRC 29
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#define EXTPCLK_CLK_SRC 30
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#define VSYNC_CLK_SRC 31
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#define HDMI_CLK_SRC 32
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#define BYTE0_CLK_SRC 33
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#define BYTE1_CLK_SRC 34
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#define ESC0_CLK_SRC 35
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#define ESC1_CLK_SRC 36
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#define CAMSS_GP0_CLK_SRC 37
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#define CAMSS_GP1_CLK_SRC 38
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#define MCLK0_CLK_SRC 39
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#define MCLK1_CLK_SRC 40
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#define MCLK2_CLK_SRC 41
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#define MCLK3_CLK_SRC 42
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#define CCI_CLK_SRC 43
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#define CSI0PHYTIMER_CLK_SRC 44
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#define CSI1PHYTIMER_CLK_SRC 45
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#define CSI2PHYTIMER_CLK_SRC 46
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#define CSIPHY0_3P_CLK_SRC 47
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#define CSIPHY1_3P_CLK_SRC 48
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#define CSIPHY2_3P_CLK_SRC 49
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#define JPEG0_CLK_SRC 50
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#define JPEG2_CLK_SRC 51
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#define JPEG_DMA_CLK_SRC 52
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#define VFE0_CLK_SRC 53
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#define VFE1_CLK_SRC 54
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#define CPP_CLK_SRC 55
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#define CSI0_CLK_SRC 56
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#define CSI1_CLK_SRC 57
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#define CSI2_CLK_SRC 58
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#define CSI3_CLK_SRC 59
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#define FD_CORE_CLK_SRC 60
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#define MMSS_CXO_CLK 61
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#define MMSS_SLEEPCLK_CLK 62
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#define MMSS_MMAGIC_AHB_CLK 63
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#define MMSS_MMAGIC_CFG_AHB_CLK 64
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#define MMSS_MISC_AHB_CLK 65
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#define MMSS_MISC_CXO_CLK 66
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#define MMSS_BTO_AHB_CLK 67
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#define MMSS_MMAGIC_AXI_CLK 68
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#define MMSS_S0_AXI_CLK 69
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#define MMSS_MMAGIC_MAXI_CLK 70
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#define DSA_CORE_CLK 71
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#define DSA_NOC_CFG_AHB_CLK 72
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#define MMAGIC_CAMSS_AXI_CLK 73
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#define MMAGIC_CAMSS_NOC_CFG_AHB_CLK 74
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#define THROTTLE_CAMSS_CXO_CLK 75
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#define THROTTLE_CAMSS_AHB_CLK 76
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#define THROTTLE_CAMSS_AXI_CLK 77
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#define SMMU_VFE_AHB_CLK 78
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#define SMMU_VFE_AXI_CLK 79
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#define SMMU_CPP_AHB_CLK 80
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#define SMMU_CPP_AXI_CLK 81
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#define SMMU_JPEG_AHB_CLK 82
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#define SMMU_JPEG_AXI_CLK 83
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#define MMAGIC_MDSS_AXI_CLK 84
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#define MMAGIC_MDSS_NOC_CFG_AHB_CLK 85
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#define THROTTLE_MDSS_CXO_CLK 86
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#define THROTTLE_MDSS_AHB_CLK 87
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#define THROTTLE_MDSS_AXI_CLK 88
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#define SMMU_ROT_AHB_CLK 89
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#define SMMU_ROT_AXI_CLK 90
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#define SMMU_MDP_AHB_CLK 91
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#define SMMU_MDP_AXI_CLK 92
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#define MMAGIC_VIDEO_AXI_CLK 93
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#define MMAGIC_VIDEO_NOC_CFG_AHB_CLK 94
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#define THROTTLE_VIDEO_CXO_CLK 95
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#define THROTTLE_VIDEO_AHB_CLK 96
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#define THROTTLE_VIDEO_AXI_CLK 97
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#define SMMU_VIDEO_AHB_CLK 98
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#define SMMU_VIDEO_AXI_CLK 99
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#define MMAGIC_BIMC_AXI_CLK 100
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#define MMAGIC_BIMC_NOC_CFG_AHB_CLK 101
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#define GPU_GX_GFX3D_CLK 102
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#define GPU_GX_RBBMTIMER_CLK 103
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#define GPU_AHB_CLK 104
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#define GPU_AON_ISENSE_CLK 105
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#define VMEM_MAXI_CLK 106
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#define VMEM_AHB_CLK 107
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#define MMSS_RBCPR_CLK 108
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#define MMSS_RBCPR_AHB_CLK 109
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#define VIDEO_CORE_CLK 110
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#define VIDEO_AXI_CLK 111
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#define VIDEO_MAXI_CLK 112
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#define VIDEO_AHB_CLK 113
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#define VIDEO_SUBCORE0_CLK 114
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#define VIDEO_SUBCORE1_CLK 115
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#define MDSS_AHB_CLK 116
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#define MDSS_HDMI_AHB_CLK 117
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#define MDSS_AXI_CLK 118
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#define MDSS_PCLK0_CLK 119
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#define MDSS_PCLK1_CLK 120
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#define MDSS_MDP_CLK 121
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#define MDSS_EXTPCLK_CLK 122
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#define MDSS_VSYNC_CLK 123
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#define MDSS_HDMI_CLK 124
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#define MDSS_BYTE0_CLK 125
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#define MDSS_BYTE1_CLK 126
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#define MDSS_ESC0_CLK 127
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#define MDSS_ESC1_CLK 128
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#define CAMSS_TOP_AHB_CLK 129
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#define CAMSS_AHB_CLK 130
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#define CAMSS_MICRO_AHB_CLK 131
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#define CAMSS_GP0_CLK 132
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#define CAMSS_GP1_CLK 133
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#define CAMSS_MCLK0_CLK 134
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#define CAMSS_MCLK1_CLK 135
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#define CAMSS_MCLK2_CLK 136
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#define CAMSS_MCLK3_CLK 137
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#define CAMSS_CCI_CLK 138
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#define CAMSS_CCI_AHB_CLK 139
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#define CAMSS_CSI0PHYTIMER_CLK 140
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#define CAMSS_CSI1PHYTIMER_CLK 141
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#define CAMSS_CSI2PHYTIMER_CLK 142
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#define CAMSS_CSIPHY0_3P_CLK 143
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#define CAMSS_CSIPHY1_3P_CLK 144
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#define CAMSS_CSIPHY2_3P_CLK 145
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#define CAMSS_JPEG0_CLK 146
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#define CAMSS_JPEG2_CLK 147
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#define CAMSS_JPEG_DMA_CLK 148
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#define CAMSS_JPEG_AHB_CLK 149
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#define CAMSS_JPEG_AXI_CLK 150
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#define CAMSS_VFE_AHB_CLK 151
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#define CAMSS_VFE_AXI_CLK 152
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#define CAMSS_VFE0_CLK 153
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#define CAMSS_VFE0_STREAM_CLK 154
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#define CAMSS_VFE0_AHB_CLK 155
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#define CAMSS_VFE1_CLK 156
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#define CAMSS_VFE1_STREAM_CLK 157
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#define CAMSS_VFE1_AHB_CLK 158
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#define CAMSS_CSI_VFE0_CLK 159
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#define CAMSS_CSI_VFE1_CLK 160
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#define CAMSS_CPP_VBIF_AHB_CLK 161
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#define CAMSS_CPP_AXI_CLK 162
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#define CAMSS_CPP_CLK 163
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#define CAMSS_CPP_AHB_CLK 164
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#define CAMSS_CSI0_CLK 165
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#define CAMSS_CSI0_AHB_CLK 166
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#define CAMSS_CSI0PHY_CLK 167
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#define CAMSS_CSI0RDI_CLK 168
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#define CAMSS_CSI0PIX_CLK 169
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#define CAMSS_CSI1_CLK 170
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#define CAMSS_CSI1_AHB_CLK 171
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#define CAMSS_CSI1PHY_CLK 172
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#define CAMSS_CSI1RDI_CLK 173
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#define CAMSS_CSI1PIX_CLK 174
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#define CAMSS_CSI2_CLK 175
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#define CAMSS_CSI2_AHB_CLK 176
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#define CAMSS_CSI2PHY_CLK 177
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#define CAMSS_CSI2RDI_CLK 178
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#define CAMSS_CSI2PIX_CLK 179
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#define CAMSS_CSI3_CLK 180
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#define CAMSS_CSI3_AHB_CLK 181
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#define CAMSS_CSI3PHY_CLK 182
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#define CAMSS_CSI3RDI_CLK 183
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#define CAMSS_CSI3PIX_CLK 184
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#define CAMSS_ISPIF_AHB_CLK 185
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#define FD_CORE_CLK 186
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#define FD_CORE_UAR_CLK 187
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#define FD_AHB_CLK 188
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#define MMSS_SPDM_CSI0_CLK 189
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#define MMSS_SPDM_JPEG_DMA_CLK 190
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#define MMSS_SPDM_CPP_CLK 191
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#define MMSS_SPDM_PCLK0_CLK 192
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#define MMSS_SPDM_AHB_CLK 193
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#define MMSS_SPDM_GFX3D_CLK 194
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#define MMSS_SPDM_PCLK1_CLK 195
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#define MMSS_SPDM_JPEG2_CLK 196
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#define MMSS_SPDM_DEBUG_CLK 197
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#define MMSS_SPDM_VFE1_CLK 198
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#define MMSS_SPDM_VFE0_CLK 199
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#define MMSS_SPDM_VIDEO_CORE_CLK 200
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#define MMSS_SPDM_AXI_CLK 201
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#define MMSS_SPDM_MDP_CLK 202
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#define MMSS_SPDM_JPEG0_CLK 203
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#define MMSS_SPDM_RM_AXI_CLK 204
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#define MMSS_SPDM_RM_MAXI_CLK 205
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#define MMAGICAHB_BCR 0
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#define MMAGIC_CFG_BCR 1
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#define MISC_BCR 2
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#define BTO_BCR 3
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#define MMAGICAXI_BCR 4
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#define MMAGICMAXI_BCR 5
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#define DSA_BCR 6
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#define MMAGIC_CAMSS_BCR 7
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#define THROTTLE_CAMSS_BCR 8
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#define SMMU_VFE_BCR 9
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#define SMMU_CPP_BCR 10
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#define SMMU_JPEG_BCR 11
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#define MMAGIC_MDSS_BCR 12
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#define THROTTLE_MDSS_BCR 13
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#define SMMU_ROT_BCR 14
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#define SMMU_MDP_BCR 15
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#define MMAGIC_VIDEO_BCR 16
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#define THROTTLE_VIDEO_BCR 17
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#define SMMU_VIDEO_BCR 18
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#define MMAGIC_BIMC_BCR 19
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#define GPU_GX_BCR 20
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#define GPU_BCR 21
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#define GPU_AON_BCR 22
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#define VMEM_BCR 23
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#define MMSS_RBCPR_BCR 24
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#define VIDEO_BCR 25
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#define MDSS_BCR 26
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#define CAMSS_TOP_BCR 27
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#define CAMSS_AHB_BCR 28
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#define CAMSS_MICRO_BCR 29
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#define CAMSS_CCI_BCR 30
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#define CAMSS_PHY0_BCR 31
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#define CAMSS_PHY1_BCR 32
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#define CAMSS_PHY2_BCR 33
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#define CAMSS_CSIPHY0_3P_BCR 34
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#define CAMSS_CSIPHY1_3P_BCR 35
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#define CAMSS_CSIPHY2_3P_BCR 36
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#define CAMSS_JPEG_BCR 37
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#define CAMSS_VFE_BCR 38
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#define CAMSS_VFE0_BCR 39
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#define CAMSS_VFE1_BCR 40
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#define CAMSS_CSI_VFE0_BCR 41
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#define CAMSS_CSI_VFE1_BCR 42
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#define CAMSS_CPP_TOP_BCR 43
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#define CAMSS_CPP_BCR 44
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#define CAMSS_CSI0_BCR 45
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#define CAMSS_CSI0RDI_BCR 46
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#define CAMSS_CSI0PIX_BCR 47
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#define CAMSS_CSI1_BCR 48
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#define CAMSS_CSI1RDI_BCR 49
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#define CAMSS_CSI1PIX_BCR 50
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#define CAMSS_CSI2_BCR 51
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#define CAMSS_CSI2RDI_BCR 52
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#define CAMSS_CSI2PIX_BCR 53
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#define CAMSS_CSI3_BCR 54
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#define CAMSS_CSI3RDI_BCR 55
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#define CAMSS_CSI3PIX_BCR 56
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#define CAMSS_ISPIF_BCR 57
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#define FD_BCR 58
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#define MMSS_SPDM_RM_BCR 59
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/* Indexes for GDSCs */
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#define MMAGIC_VIDEO_GDSC 0
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#define MMAGIC_MDSS_GDSC 1
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#define MMAGIC_CAMSS_GDSC 2
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#define GPU_GDSC 3
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#define VENUS_GDSC 4
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#define VENUS_CORE0_GDSC 5
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#define VENUS_CORE1_GDSC 6
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#define CAMSS_GDSC 7
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#define VFE0_GDSC 8
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#define VFE1_GDSC 9
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#define JPEG_GDSC 10
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#define CPP_GDSC 11
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#define FD_GDSC 12
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#define MDSS_GDSC 13
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#define GPU_GX_GDSC 14
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#define MMAGIC_BIMC_GDSC 15
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#endif
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