/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (C) 2020 Intel Corporation.
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* Lei Chuanhua <Chuanhua.lei@intel.com>
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* Zhu Yixin <Yixin.zhu@intel.com>
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*/
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#ifndef __INTEL_LGM_CLK_H
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#define __INTEL_LGM_CLK_H
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/* PLL clocks */
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#define LGM_CLK_OSC 1
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#define LGM_CLK_PLLPP 2
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#define LGM_CLK_PLL2 3
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#define LGM_CLK_PLL0CZ 4
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#define LGM_CLK_PLL0B 5
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#define LGM_CLK_PLL1 6
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#define LGM_CLK_LJPLL3 7
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#define LGM_CLK_LJPLL4 8
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#define LGM_CLK_PLL0CM0 9
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#define LGM_CLK_PLL0CM1 10
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/* clocks from PLLs */
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/* ROPLL clocks */
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#define LGM_CLK_PP_HW 15
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#define LGM_CLK_PP_UC 16
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#define LGM_CLK_PP_FXD 17
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#define LGM_CLK_PP_TBM 18
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/* PLL2 clocks */
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#define LGM_CLK_DDR 20
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/* PLL0CZ */
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#define LGM_CLK_CM 25
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#define LGM_CLK_IC 26
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#define LGM_CLK_SDXC3 27
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/* PLL0B */
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#define LGM_CLK_NGI 30
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#define LGM_CLK_NOC4 31
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#define LGM_CLK_SW 32
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#define LGM_CLK_QSPI 33
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#define LGM_CLK_CQEM LGM_CLK_SW
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#define LGM_CLK_EMMC5 LGM_CLK_NOC4
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/* PLL1 */
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#define LGM_CLK_CT 35
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#define LGM_CLK_DSP 36
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#define LGM_CLK_VIF 37
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/* LJPLL3 */
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#define LGM_CLK_CML 40
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#define LGM_CLK_SERDES 41
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#define LGM_CLK_POOL 42
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#define LGM_CLK_PTP 43
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/* LJPLL4 */
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#define LGM_CLK_PCIE 45
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#define LGM_CLK_SATA LGM_CLK_PCIE
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/* PLL0CM0 */
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#define LGM_CLK_CPU0 50
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/* PLL0CM1 */
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#define LGM_CLK_CPU1 55
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/* Miscellaneous clocks */
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#define LGM_CLK_EMMC4 60
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#define LGM_CLK_SDXC2 61
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#define LGM_CLK_EMMC 62
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#define LGM_CLK_SDXC 63
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#define LGM_CLK_SLIC 64
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#define LGM_CLK_DCL 65
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#define LGM_CLK_DOCSIS 66
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#define LGM_CLK_PCM 67
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#define LGM_CLK_DDR_PHY 68
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#define LGM_CLK_PONDEF 69
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#define LGM_CLK_PL25M 70
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#define LGM_CLK_PL10M 71
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#define LGM_CLK_PL1544K 72
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#define LGM_CLK_PL2048K 73
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#define LGM_CLK_PL8K 74
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#define LGM_CLK_PON_NTR 75
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#define LGM_CLK_SYNC0 76
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#define LGM_CLK_SYNC1 77
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#define LGM_CLK_PROGDIV 78
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#define LGM_CLK_OD0 79
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#define LGM_CLK_OD1 80
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#define LGM_CLK_CBPHY0 81
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#define LGM_CLK_CBPHY1 82
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#define LGM_CLK_CBPHY2 83
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#define LGM_CLK_CBPHY3 84
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/* Gate clocks */
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/* Gate CLK0 */
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#define LGM_GCLK_C55 100
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#define LGM_GCLK_QSPI 101
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#define LGM_GCLK_EIP197 102
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#define LGM_GCLK_VAULT 103
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#define LGM_GCLK_TOE 104
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#define LGM_GCLK_SDXC 105
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#define LGM_GCLK_EMMC 106
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#define LGM_GCLK_SPI_DBG 107
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#define LGM_GCLK_DMA3 108
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/* Gate CLK1 */
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#define LGM_GCLK_DMA0 120
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#define LGM_GCLK_LEDC0 121
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#define LGM_GCLK_LEDC1 122
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#define LGM_GCLK_I2S0 123
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#define LGM_GCLK_I2S1 124
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#define LGM_GCLK_EBU 125
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#define LGM_GCLK_PWM 126
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#define LGM_GCLK_I2C0 127
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#define LGM_GCLK_I2C1 128
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#define LGM_GCLK_I2C2 129
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#define LGM_GCLK_I2C3 130
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#define LGM_GCLK_SSC0 131
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#define LGM_GCLK_SSC1 132
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#define LGM_GCLK_SSC2 133
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#define LGM_GCLK_SSC3 134
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#define LGM_GCLK_GPTC0 135
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#define LGM_GCLK_GPTC1 136
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#define LGM_GCLK_GPTC2 137
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#define LGM_GCLK_GPTC3 138
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#define LGM_GCLK_ASC0 139
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#define LGM_GCLK_ASC1 140
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#define LGM_GCLK_ASC2 141
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#define LGM_GCLK_ASC3 142
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#define LGM_GCLK_PCM0 143
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#define LGM_GCLK_PCM1 144
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#define LGM_GCLK_PCM2 145
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/* Gate CLK2 */
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#define LGM_GCLK_PCIE10 150
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#define LGM_GCLK_PCIE11 151
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#define LGM_GCLK_PCIE30 152
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#define LGM_GCLK_PCIE31 153
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#define LGM_GCLK_PCIE20 154
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#define LGM_GCLK_PCIE21 155
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#define LGM_GCLK_PCIE40 156
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#define LGM_GCLK_PCIE41 157
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#define LGM_GCLK_XPCS0 158
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#define LGM_GCLK_XPCS1 159
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#define LGM_GCLK_XPCS2 160
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#define LGM_GCLK_XPCS3 161
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#define LGM_GCLK_SATA0 162
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#define LGM_GCLK_SATA1 163
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#define LGM_GCLK_SATA2 164
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#define LGM_GCLK_SATA3 165
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/* Gate CLK3 */
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#define LGM_GCLK_ARCEM4 170
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#define LGM_GCLK_IDMAR1 171
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#define LGM_GCLK_IDMAT0 172
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#define LGM_GCLK_IDMAT1 173
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#define LGM_GCLK_IDMAT2 174
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#define LGM_GCLK_PPV4 175
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#define LGM_GCLK_GSWIPO 176
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#define LGM_GCLK_CQEM 177
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#define LGM_GCLK_XPCS5 178
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#define LGM_GCLK_USB1 179
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#define LGM_GCLK_USB2 180
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#endif /* __INTEL_LGM_CLK_H */
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