/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
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*/
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#ifndef __DTS_HI3516CV300_CLOCK_H
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#define __DTS_HI3516CV300_CLOCK_H
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/* hi3516CV300 core CRG */
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#define HI3516CV300_APB_CLK 0
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#define HI3516CV300_UART0_CLK 1
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#define HI3516CV300_UART1_CLK 2
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#define HI3516CV300_UART2_CLK 3
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#define HI3516CV300_SPI0_CLK 4
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#define HI3516CV300_SPI1_CLK 5
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#define HI3516CV300_FMC_CLK 6
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#define HI3516CV300_MMC0_CLK 7
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#define HI3516CV300_MMC1_CLK 8
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#define HI3516CV300_MMC2_CLK 9
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#define HI3516CV300_MMC3_CLK 10
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#define HI3516CV300_ETH_CLK 11
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#define HI3516CV300_ETH_MACIF_CLK 12
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#define HI3516CV300_DMAC_CLK 13
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#define HI3516CV300_PWM_CLK 14
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#define HI3516CV300_USB2_BUS_CLK 15
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#define HI3516CV300_USB2_OHCI48M_CLK 16
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#define HI3516CV300_USB2_OHCI12M_CLK 17
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#define HI3516CV300_USB2_OTG_UTMI_CLK 18
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#define HI3516CV300_USB2_HST_PHY_CLK 19
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#define HI3516CV300_USB2_UTMI0_CLK 20
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#define HI3516CV300_USB2_PHY_CLK 21
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/* hi3516CV300 sysctrl CRG */
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#define HI3516CV300_WDT_CLK 1
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#endif /* __DTS_HI3516CV300_CLOCK_H */
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